An accurate simulation framework for thermal explorations and optimizations
Article No.: 5, Pages 1 - 6
Abstract
While technology scaling allows to integrate more cores in the same chip, the complexity of current designs requires accurate and fast techniques to explore different trade-offs. Moreover, the increased power densities in current architectures highlight thermal issues as a first class design metric to be addressed. At the same time, the need to access to accurate models for the exploited actuators is of paramount importance, since their overheads can shadow the benefit of the proposed methodologies. This paper proposes a complete simulation framework for the assessment of run-time policies for thermal-performance and power-performance trade-offs optimization with two main improvements over the state of the art. First, it accurately models Dynamic Voltage and Frequency Scaling (DVFS) modules for both cores and NoC routers as well as a complete Globally Asynchronous Locally Synchronous (GALS) design paradigm and power gating support for crossabar and buffers in the NoC. Second, it accounts for the chip thermal dynamics as well as power and performance overheads for the actuators.
References
[1]
A. Bartolini, M. Cacciari, A. Tilli, L. Benini, and M. Gries. A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores. In GLSVLSI'10, pages 311--316, New York, NY, USA, 2010. ACM.
[2]
N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood. The gem5 simulator. SIGARCH Comput. Archit. News, 39(2):1--7, Aug. 2011.
[3]
D. Brooks, V. Tiwari, and M. Martonosi. Wattch: a framework for architectural-level power analysis and optimizations. In Proceedings of the 27th annual international symposium on Computer architecture, ISCA, pages 83--94, New York, NY, USA, 2000. ACM.
[4]
T. Carlson, W. Heirman, and L. Eeckhout. Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation. In High Performance Computing, Networking, Storage and Analysis (SC), 2011 International Conference for, pages 1--12, 2011.
[5]
J. Donald and M. Martonosi. Techniques for multicore thermal management: Classification and new exploration. In Computer Architecture. ISCA '06. 33rd International Symposium on, pages 78--88, 2006.
[6]
M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. Mibench: A free, commercially representative embedded benchmark suite. In Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop, WWC '01, pages 3--14, Washington, DC, USA, 2001. IEEE Computer Society.
[7]
H. Hanson, S. Keckler, S. Ghiasi, K. Rajamani, F. Rawson, and J. Rubio. Thermal response to dvfs: analysis with an intel pentium m. In Low Power Electronics and Design (ISLPED), ACM/IEEE International Symposium on, pages 219--224, 2007.
[8]
M.-y. Hsieh, A. Rodrigues, R. Riesen, K. Thompson, and W. Song. A framework for architecture-level power, area, and thermal simulation and its application to network-on-chip design exploration. SIGMETRICS Perform. Eval. Rev., 38: 63--68, 2011.
[9]
W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, and M. Stan. Hotspot: a compact thermal modeling methodology for early-stage vlsi design. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 14(5): 501--513, May 2006.
[10]
A. Kahng, B. Li, L.-S. Peh, and K. Samadi. Orion 2.0: A fast and accurate noc power and area model for early-stage design space exploration. In Design, Automation Test in Europe Conference Exhibition, 2009. DATE '09., pages 423--428, April 2009.
[11]
S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi. The mcpat framework for multicore and manycore architectures: Simultaneously modeling power, area, and timing. ACM Trans. Archit. Code Optim., 10(1): 5:1--5:29, Apr. 2013.
[12]
N. Muralimanohar, R. Balasubramonian, and N. Jouppi. Architecting efficient interconnects for large caches with cacti 6.0. Micro, IEEE, 28(1): 69--79, Jan 2008.
[13]
S. Prabhu, B. Grot, P. V. Gratz, and J. Hu. 1 ocin tsim- dvfs aware simulator for nocs.
[14]
A. Tiwari and J. Torrellas. Facelift: Hiding and slowing down aging in multicores. In Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 41, pages 129--140, Washington, DC, USA, 2008. IEEE Computer Society.
[15]
D. Zoni, S. Corbetta, and W. Fornaciari. Hands: heterogeneous architectures and networks-on-chip design and simulation. In Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, ISLPED '12, pages 261--266, New York, NY, USA, 2012. ACM.
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- An accurate simulation framework for thermal explorations and optimizations
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Published In
January 2015
60 pages
ISBN:9781605586991
DOI:10.1145/2693433
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Association for Computing Machinery
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Published: 19 January 2015
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