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Challenges in low-power analog circuit design for sub-28nm CMOS technologies

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Amr FahimAuthors Info & Claims

ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design

Pages 123 - 126

https://doi.org/10.1145/2627369.2631639

Published: 11 August 2014 Publication History

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Abstract

In this paper, we discuss some of the most pressing challenges in low-power analog circuit design for sub-28nm technologies. A design methodology suitable for deep submicron low-power analog design is first described. Using the proposed figure of merit, several technologies as they scale down towards 28nm are compared. This is followed by a discussion of some of the issues that are unique to 28nm CMOS technologies and beyond. The effect of FinFETs devices in analog circuit design is also explored.

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https://doi.org/10.1109/ACCESS.2024.3469090
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Mah SKer PAhmad IZainul Abidin NAli Gamel M(2021)A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-LengthMaterials10.3390/ma1419572114:19(5721)Online publication date: 30-Sep-2021
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Index Terms

Challenges in low-power analog circuit design for sub-28nm CMOS technologies
1. Hardware
  1. Integrated circuits

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Published In

ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design

August 2014

398 pages

ISBN:9781450329750

DOI:10.1145/2627369

General Chairs:
Yuan Xie
UCSB, USA
,
Tanay Karnik
Intel, USA
,
Program Chairs:
Muhammad M. Khellah
Intel, USA
,
Renu Mehra
Synopsys, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 11 August 2014

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ISLPED'14: International Symposium on Low Power Electronics and Design

August 11 - 13, 2014

California, La Jolla, USA

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ISLPED '14 Paper Acceptance Rate 63 of 184 submissions, 34%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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https://doi.org/10.1109/ACCESS.2024.3469090
De La Houssaye PMauger JBulsara AHutchens CMigliori B(2023)Noise Driven Coupled Nonlinear Systems: A “Dynamical Multilayer Perceptron” Demonstrating XOR FunctionalityIEEE Access10.1109/ACCESS.2023.334416111(144306-144324)Online publication date: 2023
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Sub 1-V highly-linear low-power class-AB bulk-driven tunable CMOS transconductor

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