research-article

HEX: scaling honeycombs is easier than scaling clock trees

Authors:

Matthias Függer,

Christoph Lenzen,

Ulrich SchmidAuthors Info & Claims

SPAA '13: Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures

Pages 164 - 175

https://doi.org/10.1145/2486159.2486192

Published: 23 July 2013 Publication History

Abstract

We argue that grid structures are a very promising alternative to the standard approach for distributing a clock signal throughout VLSI circuits and other hardware devices. Traditionally, this is accomplished by a delay-balanced clock tree, which distributes the signal supplied by a single clock source via carefully engineered and buffered signal paths.

Our approach, termed HEX, is based on a hexagonal grid with simple intermediate nodes, which both control the forwarding of clock ticks in the grid and supply them to nearby functional units. HEX is Byzantine fault-tolerant, in a way that scales with the grid size, self-stabilizing, and seamlessly integrates with multiple synchronized clock sources, as used in multi-synchronous Globally Synchronous Locally Asynchronous (GALS) architectures. Moreover, HEX guarantees a small clock skew between neighbors even for wire delays that are only moderately balanced. We provide both a theoretical analysis of the worst-case skew and simulation results that demonstrate very small typical skew in realistic runs.

References

[1]

R. Bhamidipati, A. Zaidi, S. Makineni, K. Low, R. Chen, K.-Y. Liu, and J. Dalgrehn. Challenges and Methodologies for Implementing High-Performance Network Processors. Intel Technology Journal, 6(3):83--92, 2002.

[2]

D. M. Chapiro. Globally-Asynchronous Locally-Synchronous Systems. PhD thesis, Stanford University, 1984.

Digital Library

[3]

E. W. Dijkstra. Self-Stabilizing Systems in Spite of Distributed Control. Communications of the ACM, 17(11):643--644, 1974.

Digital Library

[4]

C. Dike and E. Burton. Miller and Noise Effects in a Synchronizing Flip-Flop. IEEE Journal of Solid-State Circuits, SC-34(6):849--855, 1999.

[5]

D. Dolev, M. Függer, C. Lenzen, and U. Schmid. Fault-Tolerant Algorithms for Tick-Generation in Asynchronous Logic: Robust Pulse Generation - {Extended Abstract}. In Proc. 13th Symposium on Stabilization, Safety, and Security of Distributed Systems (SSS), pages 163--177, 2011.

Digital Library

[6]

S. Fairbanks. Method and Apparatus for a Distributed Clock Generator, 2004. US patent no. US2004108876.

[7]

S. Fairbanks and S. Moore. Self-Timed Circuitry for Global Clocking. In Proc. 11th Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 86--96, 2005.

Digital Library

[8]

E. G. Friedman. Clock Distribution Networks in Synchronous Digital Integrated Circuits. Proceedings of the IEEE, 89(5):665--692, 2001.

[9]

M. Függer, A. Dielacher, and U. Schmid. How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining. In Proc. 8th European Dependable Computing Conference (EDCC), pages 230--239, 2010.

Digital Library

[10]

M. Függer and U. Schmid. Reconciling Fault-Tolerant Distributed Computing and Systems-on-Chip. Distributed Computing, 24(6):323--355, 2012.

Digital Library

[11]

V. Gutnik and A. Chandrakasan. Active GHz Clock Network Using Distributed PLLs. IEEE Journal of Solid-State Circuits, 35(11):1553--1560, 2000.

[12]

IEEE-SA Standards Board. IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems. IEEE Std 1588--2008 (Revision of IEEE Std 1588--2002), pages c1--269, 2008.

[13]

D. J. Kinniment, A. Bystrov, and A. V. Yakovlev. Synchronization Circuit Performance. IEEE Journal of Solid-State Circuits, SC-37(2):202--209, 2002.

[14]

A. Korniienko, E. Colinet, G. Scorletti, E. Blanco, D. Galayko, and J. Juillard. A Clock Network of Distributed ADPLLs Using an Asymmetric Comparison Strategy. In Proc. 2010 Symposium on Circuits and Systems (ISCAS), pages 3212--3215, 2010.

[15]

D.-J. Lee, M.-C. Kim, and I. Markov. Low-power Clock Trees for CPUs. In Proc. 2010 Conference on Computer-Aided Design (ICCAD), pages 444--451, 2010.

Digital Library

[16]

D.-J. Lee and I. Markov. Multilevel Tree Fusion for Robust Clock Networks. In 2011 Conference on Computer-Aided Design (ICCAD), pages 632--639, 2011.

Digital Library

[17]

M. S. Maza and M. L. Aranda. Interconnected Rings and Oscillators as Gigahertz Clock Distribution Nets. In Proc. 13th Great Lakes Symposium on VLSI (GLSVLSI), pages 41--44, 2003.

Digital Library

[18]

D. G. Messerschmitt. Synchronization in Digital System Design. IEEE Journal on Selected Areas in Communications, 8(8):1404--1419, 1990.

Digital Library

[19]

C. Metra, S. Francescantonio, and T. Mak. Implications of Clock Distribution Faults and Issues with Screening them During Manufacturing Testing. IEEE Transactions on Computers, 53(5):531--546, 2004.

Digital Library

[20]

T. Polzer, T. Handl, and A. Steininger. A Metastability-Free Multi-synchronous Communication Scheme for SoCs. In Proc. 11th Symposium on Stabilization, Safety, and Security of Distributed Systems (SSS), pages 578--592, 2009.

Digital Library

[21]

C. L. Portmann and T. H. Y. Meng. Supply Noise and CMOS Synchronization Errors. IEEE Journal of Solid-State Circuits, SC-30(9):1015--1017, 1995.

[22]

S. Reddy, G. Wilke, and R. Murgai. Analyzing Timing Uncertainty in Mesh-based Clock Architectures. In Proc. Design, Automation and Test in Europe (DATE), volume 1, pages 1--6, 2006.

Digital Library

[23]

P. Restle, T. McNamara, D. Webber, P. Camporese, K. Eng, K. Jenkins, D. Allen, M. Rohn, M. Quaranta, D. Boerstler, C. Alpert, C. Carter, R. Bailey, J. Petrovick, B. Krauter, and B. McCredie. A Clock Distribution Network for Microprocessors. IEEE Journal of Solid-State Circuits, 36(5):792--799, 2001.

[24]

M. Saint-Laurent and M. Swaminathan. A Multi-PLL Clock Distribution Architecture for Gigascale Integration. In Proc. 2001 IEEE Computer Society Workshop on VLSI (WVLSI), pages 30--35, 2001.

Digital Library

[25]

Y. Semiat and R. Ginosar. Timing Measurements of Synchronization Circuits. In Proc. 9th Symposium on Asynchronous Circuits and Systems (ASYNC), 2003.

Digital Library

[26]

R. Shelar. Routing with Constraints for Post-Grid Clock Distribution in Microprocessors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(2):245--249, 2010.

Digital Library

[27]

C. N. Sze. ISPD 2010 High Performance Clock Network Synthesis Contest: Benchmark Suite and Results. In Proc. 19th Symposium on Physical Design (ISPD), pages 143--143, 2010.

Digital Library

[28]

P. Teehan, M. Greenstreet, and G. Lemieux. A Survey and Taxonomy of GALS Design Styles. IEEE Design and Test of Computers, 24(5):418--428, 2007.

Digital Library

[29]

C. Yeh, G. Wilke, H. Chen, S. Reddy, H. Nguyen, T. Miyoshi, W. Walker, and R. Murgai. Clock Distribution Architectures: a Comparative Study. In Proc. 7th Symposium on Quality Electronic Design (ISQED), pages 85--91, 2006.

Digital Library

Cited By

Függer MLenzen CSchmid U(2022)On Specifications and Proofs of Timed CircuitsPrinciples of Systems Design10.1007/978-3-031-22337-2_6(107-130)Online publication date: 29-Dec-2022
https://doi.org/10.1007/978-3-031-22337-2_6
Han KKahng ALi J(2020)Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock DistributionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288975639:2(478-491)Online publication date: Mar-2020
https://doi.org/10.1109/TCAD.2018.2889756
Nelson AGoossens KGirault AGuan N(2015)Distributed power management of real-time applications on a GALS multiprocessor SOCProceedings of the 12th International Conference on Embedded Software10.5555/2830865.2830882(147-156)Online publication date: 4-Oct-2015
https://dl.acm.org/doi/10.5555/2830865.2830882
Show More Cited By

Index Terms

HEX: scaling honeycombs is easier than scaling clock trees
1. Hardware
  1. Hardware test
  2. Robustness
2. Theory of computation
  1. Design and analysis of algorithms

Recommendations

HEX

We argue that a hexagonal grid with simple intermediate nodes is a robust alternative to buffered clock trees typically used for clock distribution in VLSI circuits, multi-core processors, and other applications that require accurate synchronization: ...
Self-stabilizing Byzantine Tolerant Replicated State Machine Based on Failure Detectors
Cyber Security Cryptography and Machine Learning
Abstract
Byzantine Fault Tolerant (BFT) replication leverages highly available cloud services and can facilitate the implementation of distributed ledgers, e.g., the blockchain. Systems providing BFT State Machine Replication (SMR) work under severe system ...
A Design Approach for Self-Diagnosis of Fault-Tolerant Clock Synchronization

A general design approach for self-diagnosis of faulty clocking modules in a fault-tolerant clock synchronization (FTCS) system is presented. The approach is based on a statistical testing method. The major advantages are better self-stability control ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

SPAA '13: Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures

July 2013

348 pages

ISBN:9781450315722

DOI:10.1145/2486159

General Chair:
Guy Blelloch
Carnegie Mellon University, USA
,
Program Chair:
Berthold Vöcking
RWTH Aachen University, Germany

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 July 2013

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

SPAA '13

Sponsor:

SPAA '13: 25th ACM Symposium on Parallelism in Algorithms and Architectures

July 23 - 25, 2013

Québec, Montréal, Canada

Acceptance Rates

SPAA '13 Paper Acceptance Rate 31 of 130 submissions, 24%;

Overall Acceptance Rate 447 of 1,461 submissions, 31%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
143
Total Downloads

Downloads (Last 12 months)5
Downloads (Last 6 weeks)1

Reflects downloads up to 28 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Függer MLenzen CSchmid U(2022)On Specifications and Proofs of Timed CircuitsPrinciples of Systems Design10.1007/978-3-031-22337-2_6(107-130)Online publication date: 29-Dec-2022
https://doi.org/10.1007/978-3-031-22337-2_6
Han KKahng ALi J(2020)Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock DistributionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288975639:2(478-491)Online publication date: Mar-2020
https://doi.org/10.1109/TCAD.2018.2889756
Nelson AGoossens KGirault AGuan N(2015)Distributed power management of real-time applications on a GALS multiprocessor SOCProceedings of the 12th International Conference on Embedded Software10.5555/2830865.2830882(147-156)Online publication date: 4-Oct-2015
https://dl.acm.org/doi/10.5555/2830865.2830882
Nelson AGoossens K(2015)Distributed power management of real-time applications on a GALS multiprocessor SOC2015 International Conference on Embedded Software (EMSOFT)10.1109/EMSOFT.2015.7318270(147-156)Online publication date: Oct-2015
https://doi.org/10.1109/EMSOFT.2015.7318270
Nelson AGoossens KAkesson B(2015)Dataflow formalisation of real-time streaming applications on a Composable and Predictable Multi-Processor SOCJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2015.04.00161:9(435-448)Online publication date: 1-Oct-2015
https://dl.acm.org/doi/10.1016/j.sysarc.2015.04.001

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents