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DRMA: dynamically reconfigurable MPSoC architecture

Published: 02 May 2013 Publication History

Abstract

Embedded systems are ubiquitous and are deployed in a large range of applications. Designing and fabricating Integrated Circuits (ICs) targeting such different range of applications is expensive. Designers seek flexible processors which efficiently execute a multitude of applications. FPGAs are considered affordable, but design cost, high reconfiguration delay and power consumption are all prohibitive. In this paper, we propose a novel ASIC based flexible MPSoC architecture, which can execute separate tasks in parallel, and it can be configured to execute single task with wide data widths or execute multiple tasks with varying data widths. The architecture presented, called Dynamically Reconfigurable MPSoC Architecture (DRMA), can be rapidly reconfigured through instructions. We present applications as case studies to showcase the flexibility and efficacy of DRMA. Results show for an additional area overhead of about 5%, the system is capable of working as four 32-bit processors, a single 128 bit processor or as a pipelined processing system.

References

[1]
F. Anjam, M. Nadeem, and S. Wong. A VLIW softcore processor with dynamically adjustable issue-slots. In 2010 International Conference on Field-Programmable Technology (FPT), pages 393--398, Dec. 2010.
[2]
G. Ansaloni, P. Bonzini, and L. Pozzi. EGRA: A coarse grained reconfigurable architectural template. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(6):1062--1074, 2011.
[3]
T. Austin, E. Larson, and D. Ernst. Simplescalar: an infrastructure for computer system modeling. IEEE Computer, 35(2):59--67, Feb 2002.
[4]
F. Bouwens, M. Berekovic, B. De Sutter, and G. Gaydadjiev. Architecture enhancements for the adres coarse-grained reconfigurable array. In Proceedings of the 3rd international conference on High performance embedded architectures and compilers, HiPEAC'08, pages 66--81. Springer-Verlag, 2008.
[5]
M. Campbell-Kelly. Chips and change: how crisis reshapes the semiconductor industry. Business History, 52(6):1017--1019, 2010.
[6]
L. H. Chen and O. T.-C. Chen. Design methodology of a hardware-efficiency VLIW architecture with highly adaptable data path. In 48th Midwest Symposium on Circuits and Systems, 2005, pages 1223--1226 Vol. 2, Aug. 2005.
[7]
K. Diefendorff, P. Dubey, R. Hochsprung, and H. Scale. Altivec extension to powerpc accelerates media processing. IEEE Micro, 20(2):85--95, Mar/Apr 2000.
[8]
T. Dorta, J. Jimenez, J. Martin, U. Bidarte, and A. Astarloa. Overview of fpga-based multiprocessor systems. In International Conference on Reconfigurable Computing and FPGAs, pages 273--278, Dec. 2009.
[9]
J. A. Fisher. Very long instruction word architectures and the ELI-512. SIGARCH Comput. Archit. News, 11(3):140--150, June 1983.
[10]
S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, and R. R. Taylor. Piperench: A reconfigurable architecture and compiler. IEEE Computer, 33(4):70--77, 2000.
[11]
L. Huang, L. Shen, Z. Wang, W. Shi, N. Xiao, and S. Ma. Sif: Overcoming the limitations of simd devices via implicit permutation. In 2010 IEEE 16th International Symposium on High Performance Computer Architecture (HPCA), pages 1--12, Jan. 2010.
[12]
M. Imai. ASIPMeister: A configurable processor core development system. In Proc. ITI of 3rd International Conference on Information & Communications Technology (ICICT 2005), Cairo, Egypt, 2005.
[13]
E. Ipek, M. Kirman, N. Kirman, and J. Martinez. Accomodating workload diversity in chip multiprocessors via adaptive core fusion. In Workshop on Complexity-Effective Design, pages 10--21, 2006.
[14]
C. Kim, S. Sethumadhavan, D. Gulati, D. Burger, M. Govindan, N. Ranganathan, and S. Keckler. Composable lightweight processors. In 40th Annual IEEE/ACM International Symposium on Microarchitecture, 2007., pages 381--394, Dec. 2007.
[15]
J. S. Kim and M. Sunwoo. Three low power asip processor designs for communications, video, and audio applications. In International Conference on Design Technology of Integrated Systems in Nanoscale Era, 2007. DTIS., pages 241--244, 2007.
[16]
C. Liang and T. Mitra. Shared reconfigurable fabric for multi-core customization. In Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pages 830--835, 2011.
[17]
B. Mei, S. Vernalde, D. Verkest, and R. Lauwereins. Design methodology for a tightly coupled vliw/reconfigurable matrix architecture: a case study. In Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, volume 2, pages 1224--1229 Vol.2, Feb. 2004.
[18]
G. Mplemenos and I. Papaefstathiou. Mplem: An 80-processor fpga based multiprocessor system. In 16th International Symposium on Field-Programmable Custom Computing Machines, 2008, pages 273--274, 2008.
[19]
J. Oliver, R. Rao, D. Franklin, F. T. Chong, and V. Akella. Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications. J. Embedded Comput., 2(2):157--166, Apr. 2006.
[20]
A. Peleg and U. Weiser. MMX technology extension to the intel architecture. IEEE Micro, 16(4):42--50, Aug. 1996.
[21]
M. Pricopi and T. Mitra. Bahurupi: A polymorphic heterogeneous multi-core architecture. ACM Trans. Archit. Code Optim., 8(4):22:1--22:21, Jan. 2012.
[22]
A. Sagheer, S. Al-Rawi, and O. Dawood. Proposing of developed advance encryption standard. In Developments in E-systems Engineering (DeSE), 2011, pages 197--202, Dec. 2011.
[23]
E. Salami and M. Valero. A vector-mu;SIMD-VLIW architecture for multimedia applications. In International Conference on Parallel Processing, 2005, pages 69--77, 2005.
[24]
G. Schewior, H. Flatt, C. Dolar, C. Banz, and H. Blume. A hardware accelerated configurable ASIP architecture for embedded real-time video-based driver assistance applications. In International Conference on Embedded Computer Systems (SAMOS), 2011, pages 209--216, 2011.
[25]
S. L. Shee and S. Parameswaran. Design methodology for pipelined heterogeneous multiprocessor system. In 44th ACM/IEEE Design Automation Conference, 2007., pages 811--816, 2007.
[26]
A. Singh, A. Kumar, T. Srikanthan, and Y. Ha. Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA. In 2010 International Conference on Field-Programmable Technology (FPT), pages 365--368, Dec. 2010.
[27]
J. Smith and G. Sohi. The microarchitecture of superscalar processors. Proceedings of the IEEE, 83(12):1609--1624, Dec. 1995.
[28]
F. Sun, S. Ravi, A. Raghunathan, and N. Jha. Application-specific heterogeneous multiprocessor synthesis using extensible processors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(9):1589--1602, 2006.
[29]
D. Talla, L. John, and D. Burger. Bottlenecks in multimedia processing with SIMD style extensions and architectural enhancements. IEEE Transactions on Computers, 52(8):1015--1031, Aug. 2003.
[30]
X. Xie, J. Williams, and N. Bergmann. Asymmetric multi-processor architecture for reconfigurable system-on-chip and operating system abstractions. In International Conference on Field-Programmable Technology, 2007. ICFPT 2007., pages 41--48, Dec. 2007.
[31]
M. Zaharuddin, R. Rahman, and M. Kassim. Technical comparison analysis of encryption algorithm on site-to-site ipsec vpn. In International Conference on Computer Applications and Industrial Electronics (ICCAIE), 2010, pages 641--645, Dec. 2010.
[32]
H. Zhong, S. Lieberman, and S. Mahlke. Extending multicore architectures to exploit hybrid parallelism in single-thread applications. In IEEE 13th International Symposium on High Performance Computer Architecture, 2007, pages 25--36, Feb. 2007.

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      cover image ACM Conferences
      GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
      May 2013
      368 pages
      ISBN:9781450320320
      DOI:10.1145/2483028
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      Published: 02 May 2013

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      Author Tags

      1. dynamical reconfiguration
      2. embedded system
      3. mpsoc
      4. multiprocessor
      5. parallelism
      6. word size variation

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