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Reducing the cost of branches

Authors:

S. McFarling,

J. HenneseyAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 14, Issue 2

Pages 396 - 403

https://doi.org/10.1145/17356.17402

Published: 01 May 1986 Publication History

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Abstract

Pipelining is the major organizational technique that computers use to reach higher single-processor performance. A fundamental disadvantage of pipelining is the loss incurred due to branches that require stalling or flushing the pipeline. Both hardware solutions and architectural changes have been proposed to overcome these problems. This paper examines a range of schemes for reducing branch cost focusing on both static (compile-time) and dynamic (hardware-assisted) prediction of branches. These schemes are investigated from quantitative performance and implementation viewpoints.¹

References

[1]

Hennessy, J.L., Jouppi, N., Baskett, F., Gross, T.R., and Gill, J., "Hardware/Software Tradeoffs for Increased Performance", Sym. on Arch. Support for Prog. Lang. and Op. Sys., ACM, March 1982.

Digital Library

Google Scholar

[2]

M. Horowitz and P. Chow, "The MIPS-X Microprocessor", Wescon/85, November, 1985.

Google Scholar

[3]

Chow, F., A Portable Machine-Independent Global Optimizer - Design and Measurements, PhD dissertation, Stanford University, December 1983.

Digital Library

Google Scholar

[4]

Clark, D., Emer, J., "A Characterization of Processor Performance in the VAX 11/780", Prec. 11th Annual Sym. on Comp. Arch., ACM/IEEE, June 1984, pp. 301-311.

Digital Library

Google Scholar

[5]

Lee, J.K.L. and Smith, AJ., "Branch Prediction Strategies and Branch Target Buffer Design", Computer, Vol. 17, No. 1, January, 1984.

Google Scholar

[6]

Morris, D. and Ibbett, R., The MU5 Computer System, Springer-Verlag, New York, 1979.

Crossref

Google Scholar

[7]

Patterson, D., "Reduced Instruction Set Computers", CACM, Vol. 28, No. 1, January, 1985, pp. 8-21.

Digital Library

Google Scholar

[8]

Hennessy, J.L. and Gross, T.R., "Postpass Code Optimization of Pipeline Constraints", ACM TOPLAS, Vol. 5, No. 3, July, 1983.

Digital Library

Google Scholar

[9]

Gross, T.R., Code Optimization of Pipeline Constraints, PhD dissertation, Stanford University, August 1983.

Digital Library

Google Scholar

[10]

Katevenis, M.G.H., Reduced Instruction Set Computer Architectures for VLSI, PhD dissertation, University of California, Berkeley, October 1983.

Digital Library

Google Scholar

Cited By

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Mendelson A(2023)The ArchitectureHandbook of Computer Architecture10.1007/978-981-15-6401-7_1-1(1-42)Online publication date: 12-Sep-2023
https://doi.org/10.1007/978-981-15-6401-7_1-1
Yao Y(2021)Reflections on Computer Pipeline Technology from an Analytical PerspectiveProceedings of the 4th International Conference on Computer Science and Software Engineering10.1145/3494885.3494911(140-145)Online publication date: 22-Oct-2021
https://dl.acm.org/doi/10.1145/3494885.3494911
Brown MPruett MBigelow RMururu GPande S(2021)Not so fast: understanding and mitigating negative impacts of compiler optimizations on code reuse gadget setsProceedings of the ACM on Programming Languages10.1145/34855315:OOPSLA(1-30)Online publication date: 15-Oct-2021
https://dl.acm.org/doi/10.1145/3485531
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Reducing the cost of branches

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Reducing the cost of branches
ISCA '86: Proceedings of the 13th annual international symposium on Computer architecture

Pipelining is the major organizational technique that computers use to reach higher single-processor performance. A fundamental disadvantage of pipelining is the loss incurred due to branches that require stalling or flushing the pipeline. Both hardware ...
Comparing software and hardware schemes for reducing the cost of branches
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Pipelining has become a common technique to increase throughput of the instruction fetch, instruction decode, and instruction execution portions of modern computers. Branch instructions disrupt the flow of instructions through the pipeline, increasing ...
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Pipelining has become a common technique to increase throughput of the instruction fetch, instruction decode, and instruction execution portions of modern computers. Branch instructions disrupt the flow of instructions through the pipeline, increasing ...

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 14, Issue 2

Special Issue: Proceedings of the 13th annual international symposium on Computer architecture (ISCA '86)

May 1986

429 pages

ISSN:0163-5964

DOI:10.1145/17356

Editor:
Hideo Aiso

Issue’s Table of Contents

ISCA '86: Proceedings of the 13th annual international symposium on Computer architecture
June 1986
454 pages
ISBN:081860719X
Chairman:
Hideo Aiso

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1986

Published in SIGARCH Volume 14, Issue 2

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Mendelson A(2023)The ArchitectureHandbook of Computer Architecture10.1007/978-981-15-6401-7_1-1(1-42)Online publication date: 12-Sep-2023
https://doi.org/10.1007/978-981-15-6401-7_1-1
Yao Y(2021)Reflections on Computer Pipeline Technology from an Analytical PerspectiveProceedings of the 4th International Conference on Computer Science and Software Engineering10.1145/3494885.3494911(140-145)Online publication date: 22-Oct-2021
https://dl.acm.org/doi/10.1145/3494885.3494911
Brown MPruett MBigelow RMururu GPande S(2021)Not so fast: understanding and mitigating negative impacts of compiler optimizations on code reuse gadget setsProceedings of the ACM on Programming Languages10.1145/34855315:OOPSLA(1-30)Online publication date: 15-Oct-2021
https://dl.acm.org/doi/10.1145/3485531
Harburg ELewis DEasterday MGerber E(2018)CheerOnACM Transactions on Computer-Human Interaction10.1145/324104325:6(1-46)Online publication date: 20-Dec-2018
https://dl.acm.org/doi/10.1145/3241043
Chang PHao EYeh TPatt Y(2016)Branch Classification: A New Mechanism for Improving Branch Predictor PerformanceInternational Journal of Parallel Programming10.1007/BF0335674524:2(133-158)Online publication date: 26-May-2016
https://doi.org/10.1007/BF03356745
LaForest CAnderson JSteffan J(2014)Approaching overhead-free execution on FPGA soft-processors2014 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2014.7082760(99-106)Online publication date: Dec-2014
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Ferger MHübner M(2014)Instruction Set Optimization for Application Specific ProcessorsReconfigurable Computing: Architectures, Tools, and Applications10.1007/978-3-319-05960-0_28(268-274)Online publication date: 2014
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Riché TGonçalves RMarker BBatory D(2012)Pushouts in software architecture designACM SIGPLAN Notices10.1145/2480361.237141548:3(84-92)Online publication date: 26-Sep-2012
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Zhang HZhang LUrtado CVauttier SHuchard M(2012)A three-level component model in component based software developmentACM SIGPLAN Notices10.1145/2480361.237141248:3(70-79)Online publication date: 26-Sep-2012
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Rayside DMontaghami VLeung FYuen AXu KJackson D(2012)Synthesizing iterators from abstraction functionsACM SIGPLAN Notices10.1145/2480361.237140748:3(31-40)Online publication date: 26-Sep-2012
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