research-article

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement

Authors:

Yiran ChenAuthors Info & Claims

DAC '08: Proceedings of the 45th annual Design Automation Conference

Pages 554 - 559

https://doi.org/10.1145/1391469.1391610

Published: 08 June 2008 Publication History

Abstract

Magnetic Random Access Memory (MRAM) has been considered as a promising memory technology due to many attractive properties. Integrating MRAM with CMOS logic may incur extra manufacture cost, due to its hybrid magnetic-CMOS fabrication process. Stacking MRAM on top of CMOS logics using 3D integration is a way to minimize this cost overhead. In this paper, we discuss the circuit design issues for MRAM, and present the MRAM cache model. Based on the model, we compare MRAM against SRAM and DRAM in terms of area, performance, and energy. Finally we conduct architectural evaluation for 3D microprocessor stacking with MRAM. The experimental results show that MRAM stacking offers competitive IPC performance with a large reduction in power consumption compared to SRAM and DRAM counterparts.

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Cited By

Jayaram RWoodruff DZhou S(2024)Streaming Algorithms with Few State ChangesProceedings of the ACM on Management of Data10.1145/36511452:2(1-28)Online publication date: 14-May-2024
https://dl.acm.org/doi/10.1145/3651145
Najafi DTabrizchi SZhou RAmel Solouki MMarshal ARoohi AAngizi S(2024)Hybrid Magneto-electric FET-CMOS Integrated Memory Design for Instant-on ComputingProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3660361(770-775)Online publication date: 12-Jun-2024
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An YTang YYi SPeng LPan XSun GLuo ZLi QZhang J(2024)StreamPIM: Streaming Matrix Computation in Racetrack Memory2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00031(297-311)Online publication date: 2-Mar-2024
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Index Terms

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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cover image ACM Conferences

DAC '08: Proceedings of the 45th annual Design Automation Conference

June 2008

993 pages

ISBN:9781605581156

DOI:10.1145/1391469

General Chair:
Limor Fix
Intel Research Pittsburgh, Pittsburgh, PA

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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The EDA Consortium
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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

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Published: 08 June 2008

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DAC '08: The 45th Annual Design Automation Conference 2008

June 8 - 13, 2008

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Jayaram RWoodruff DZhou S(2024)Streaming Algorithms with Few State ChangesProceedings of the ACM on Management of Data10.1145/36511452:2(1-28)Online publication date: 14-May-2024
https://dl.acm.org/doi/10.1145/3651145
Najafi DTabrizchi SZhou RAmel Solouki MMarshal ARoohi AAngizi S(2024)Hybrid Magneto-electric FET-CMOS Integrated Memory Design for Instant-on ComputingProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3660361(770-775)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3660361
An YTang YYi SPeng LPan XSun GLuo ZLi QZhang J(2024)StreamPIM: Streaming Matrix Computation in Racetrack Memory2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00031(297-311)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00031
Xue ZWu YEmer JSze V(2023)Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer CapacityProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623793(1347-1363)Online publication date: 28-Oct-2023
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Zhang CSun HLi SWang YChen HLiu H(2023)A Survey of Memory-Centric Energy Efficient Computer ArchitectureIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2023.329759534:10(2657-2670)Online publication date: Oct-2023
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Nguyen TLee J(2023)Sparse Code With Minimum Hamming Distance of Three for Spin-Torque Transfer Magnetic Random Access MemoryIEEE Access10.1109/ACCESS.2023.332425511(114071-114079)Online publication date: 2023
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Nguyen TLee J(2023)Improving Bit-Error-Rate Performance Using Modulation Coding Techniques for Spin-Torque Transfer Magnetic Random Access MemoryIEEE Access10.1109/ACCESS.2023.326352711(33005-33013)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3263527
Inci AIsgenc MMarculescu D(2023)Efficient Deep Learning Using Non-volatile Memory Technology in GPU ArchitecturesEmbedded Machine Learning for Cyber-Physical, IoT, and Edge Computing10.1007/978-3-031-19568-6_8(225-252)Online publication date: 1-Oct-2023
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Ni MChen LHao XLiu CZhang YLi Y(2022)Elastic adaptive prefetching for non-volatile cache in IoT terminalsIEICE Electronics Express10.1587/elex.19.2022022519:13(20220225-20220225)Online publication date: 10-Jul-2022
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