research-article

Chip placement in a reticle for multiple-project wafer fabrication

Authors:

Meng-Chiou Wu,

Rung-Bin Lin,

Shih-Cheng TsaiAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 13, Issue 1

Article No.: 22, Pages 1 - 21

https://doi.org/10.1145/1297666.1297688

Published: 06 February 2008 Publication History

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Abstract

Chip placement in a reticle is crucial to the cost of a multiproject wafer run. In this article we develop several chip placement methods based on the volume-driven compatibility optimization (VOCO) concept, which maximizes dicing compatibility among chips with large-volume requirements while minimizing reticle dimensions. Our mixed-integer linear programming models with VOCO are too complex to render good solutions for large test cases. Our B*-tree with VOCO and HQ with VOCO use 16%∼ 29% fewer wafers and 8%∼ 19% less reticle area than the hierarchical quadrisection (HQ) method proposed by Kahng et al. [2005]

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Fang ZHan JWang H(2023)Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project waferIntegration10.1016/j.vlsi.2023.03.01291(144-152)Online publication date: Jul-2023
https://doi.org/10.1016/j.vlsi.2023.03.012
Malik MTsiamis AZangl HBinder AMitra SRoshanghias A(2022)Die-Level Thinning for Flip-Chip Integration on Flexible SubstratesElectronics10.3390/electronics1106084911:6(849)Online publication date: 8-Mar-2022
https://doi.org/10.3390/electronics11060849
Lin R(2018)Variable-sized object packing and its applications to instruction cache designComputers and Electrical Engineering10.1016/j.compeleceng.2008.04.00234:5(438-444)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1016/j.compeleceng.2008.04.002
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Index Terms

Chip placement in a reticle for multiple-project wafer fabrication
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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Reviews

Reviewer: Parthasarathi Dasgupta

The fabrication costs of integrated circuits (IC) are extremely high. Multiproject wafers (MPW) are used to integrate, onto microelectronics wafers, a number of different IC designs from various teams, including designs from private firms, students, and academic researchers. This paper discusses several methods for the placement of chips in a reticle for MPW fabrication. Wu et al. introduce the MPW problem and provide a brief summary of the existing works in this area. The MPW problem is formulated as a reticle floorplanning problem for a given set of N chips, where the desired production volumes for each chip are given. The objectives include: maximizing the compatibility of the chips within each reticle; minimizing the wafer requirements; and minimizing the dimension of each reticle, or restricting it within a specified value. The work is primarily based on the concept of volume-driven compatibility optimization (VOCO), and attempts, simultaneously, to maximize the compatibility among the chips with large production volume requirements and minimize the reticle dimension. (Compatibility among chips is expressed in the form of side-to-side dicing constraints.) Three different methods for the constrained reticle floorplanning are proposed. The first, a mixed-integer linear programming (MILP) method based on VOCO, considers the constraints on the placement of chips, as well as dicing lines and the related compatibility of chips with the objective function given by the concept of VOCO. The second method, a B*-tree-based floorplanning method with VOCO, is basically a B*-tree-based compact floorplanning superposed with VOCO. The third method is an improved hierarchical quadrisection floorplanning method with VOCO. The proposed hierarchical quadrisection method provides a better upper bound on the number of wafers utilized, and is the basis of a simulated annealing-based floorplanner. The quality of the proposed methods is evaluated with detailed experimental results. The tables indicate that the proposed methods are better than some recent MPW methods, particularly in terms of minimizing wafer utilization. Online Computing Reviews Service

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cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 13, Issue 1

January 2008

496 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1297666

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 06 February 2008

Accepted: 01 August 2007

Revised: 01 August 2007

Received: 01 August 2006

Published in TODAES Volume 13, Issue 1

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Fang ZHan JWang H(2023)Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project waferIntegration10.1016/j.vlsi.2023.03.01291(144-152)Online publication date: Jul-2023
https://doi.org/10.1016/j.vlsi.2023.03.012
Malik MTsiamis AZangl HBinder AMitra SRoshanghias A(2022)Die-Level Thinning for Flip-Chip Integration on Flexible SubstratesElectronics10.3390/electronics1106084911:6(849)Online publication date: 8-Mar-2022
https://doi.org/10.3390/electronics11060849
Lin R(2018)Variable-sized object packing and its applications to instruction cache designComputers and Electrical Engineering10.1016/j.compeleceng.2008.04.00234:5(438-444)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1016/j.compeleceng.2008.04.002
Kagalwalla AGupta P(2013)Design-Aware Defect-Avoidance Floorplanning of EUV MasksIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2012.223415126:1(111-124)Online publication date: Feb-2013
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Ning LWu WZhang BZhang P(2011)A time-varying transformer outage model for on-line operational risk assessmentInternational Journal of Electrical Power & Energy Systems10.1016/j.ijepes.2010.12.01633:3(600-607)Online publication date: Mar-2011
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Reticle floorplanning of flexible chips for multi-project wafers

Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers

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Multi-project reticle floorplanning and wafer dicing

Reticle floorplanning of flexible chips for multi-project wafers

Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers

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