Formal verification of state-machines using higher-order logic
PN Loewenstein - … Conference on Computer Design: VLSI in …, 1989 - ieeexplore.ieee.org
PN Loewenstein
Proceedings 1989 IEEE International Conference on Computer Design …, 1989•ieeexplore.ieee.orgA description is given of the formalization of some state-machine theory in a higher-order
logic (HOL) theorem prover and the results obtained applying that theory. It is shown that by
building state-machine theory in HOL, the verification of state-machines is rendered much
more tractable. This is illustrated using a family of redundantly encoded serial-parallel
multipliers.<>
logic (HOL) theorem prover and the results obtained applying that theory. It is shown that by
building state-machine theory in HOL, the verification of state-machines is rendered much
more tractable. This is illustrated using a family of redundantly encoded serial-parallel
multipliers.<>
A description is given of the formalization of some state-machine theory in a higher-order logic (HOL) theorem prover and the results obtained applying that theory. It is shown that by building state-machine theory in HOL, the verification of state-machines is rendered much more tractable. This is illustrated using a family of redundantly encoded serial-parallel multipliers.< >
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