Integrated circuits (IC) targeting at the streaming applications for tomorrow are becoming a fast growing market. Applications such as beamforming require mass computing capability on a single chip as well as flexibility to adapt to new algorithms. A reconfigurable IC with many processing tiles based on the Network-on-Chip architecture is considered ideal for such applications as it balances efficiency and flexibility. Due to the highly regular arrangement of the processing tiles connected by the communication network, it is possible to adopt new Design-for-X strategies to improve the dependability of the reconfigurable IC. The communication network can be reused as a test-access mechanism. On-chip deterministic test pattern generators can multicast test-vectors through the network to the cores under test and test responses from multiple cores can be collected and analyzed by a test result evaluator. The faulty core, or functional parts of it, will be labeled and isolated from the whole system by re-mapping the computing resources and thus improve the dependability of the whole system.