[BOOK][B] Technology Mapping for LUT-based FPGA

M Kubica, A Opara, D Kania - 2021 - Springer
… This book is an attempt to present a series of original concepts of technology mapping of
digital circuits in FPGAs. The process of technology mapping is closely related to the process of …

Improvements to technology mapping for LUT-based FPGAs

A Mishchenko, S Chatterjee, R Brayton - … of the 2006 ACM/SIGDA 14th …, 2006 - dl.acm.org
… (FPGAs) are an attractive hardware design option, making technology mapping for FPGAs
an … For an excellent overview of the classical and recent work on FPGA technology mapping, …

Heuristics for area minimization in LUT-based FPGA technology mapping

V Manohararajah, SD Brown… - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
… during the mapping process. Most of the existing literature [1] on technology mapping uses
the … Technology mapping is often treated as a covering problem. For example, consider the …

[PDF][PDF] On area/depth trade-off in LUT-based FPGA technology mapping

J Cong, Y Ding - Proceedings of the 30th International Design …, 1993 - dl.acm.org
mapping … It remains open if the area-optimal mapping problem for LUTbased FPGAs can
be solved efficiently. The common … for KLUT based FPGA designs is to cover the network …

A new retiming-based technology mapping algorithm for LUT-based FPGAs

P Pan, CC Lin - Proceedings of the 1998 ACM/SIGDA sixth …, 1998 - dl.acm.org
… In this paper, we proposed a,new technology mapping algorithm for LUT-based FPGAs.
The algorithm is based on a novel iterative procedure to compute all k-cuts of all nodes in a …

Power-aware technology mapping for LUT-based FPGAs

JH Anderson, FN Najm - … on Field-Programmable Technology …, 2002 - ieeexplore.ieee.org
… We present a new power-aware technology mapping techniqire for LUT-based FPGAs which
aims to keep nets with high switching activity out of the FPGA roirring nehvork and takes an …

Placement-driven technology mapping for LUT-based FPGAs

JY Lin, A Jagannathan, J Cong - Proceedings of the 2003 ACM/SIGDA …, 2003 - dl.acm.org
… We have implemented our algorithm in a LUT based FPGA technology mapping package
named PDM (Placement-Driven Mapping) and tested the implementation on a set of MCNC …

Power minization in LUT-based FPGA technology mapping

ZH Wang, EC Liu, J Lai, TC Wang - Proceedings of the 2001 Asia and …, 2001 - dl.acm.org
… , LUT-based FPGA technology mapping for power minimization considered in this paper is
to find a technology mapping … the power consumption of the mapping solution is as small as …

LUT-based FPGA technology mapping for reliability

J Cong, K Minkovich - Proceedings of the 47th Design Automation …, 2010 - dl.acm.org
… of how configuration bit errors propagate in LUT-based FPGAs. This will show that most …
technology mapper that can improve the reliability of a circuit. The results from the technology

[PDF][PDF] Edge-Map: Optimal performance driven technology mapping for iterative LUT based FPGA designs

H Yang, DF Wong - Proceedings of the 1994 IEEE/ACM …, 1994 - websrv.cecs.uci.edu
… In this paper, we present an e cient technology mapping algorithm that achieves provably …
a LUT based FPGA technology mapping package called Edge-Map, and tested Edge-Map on …