User profiles for Peter A. Beerel
Peter BeerelProfessor of Electrical and Computer Engineering, USC Verified email at usc.edu Cited by 6091 |
[BOOK][B] A designer's guide to asynchronous VLSI
PA Beerel, RO Ozdag, M Ferretti - 2010 - books.google.com
Create low power, higher performance circuits with shorter design times using this practical
guide to asynchronous design. This practical alternative to conventional synchronous design …
guide to asynchronous design. This practical alternative to conventional synchronous design …
Slack matching asynchronous designs
Slack matching is the problem of adding pipeline buffers to an asynchronous pipelined design
in order to prevent stalls and improve performance. This paper addresses the problem of …
in order to prevent stalls and improve performance. This paper addresses the problem of …
[BOOK][B] CAD tools for the synthesis, verification, and testability of robust asynchronous circuits
PA Beerel - 1994 - search.proquest.com
INFORMATION TO USERS Page 1 INFORMATION TO USERS This manuscript has been
reproduced from the microfilm master. UMI films the text directly from the original or copy …
reproduced from the microfilm master. UMI films the text directly from the original or copy …
Spike-thrift: Towards energy-efficient deep spiking neural networks by limiting spiking activity via attention-guided compression
The increasing demand for on-chip edge intelligence has motivated the exploration of
algorithmic techniques and specialized hardware to reduce the computing energy of current …
algorithmic techniques and specialized hardware to reduce the computing energy of current …
Hire-snn: Harnessing the inherent robustness of energy-efficient deep spiking neural networks by training with crafted input noise
Low-latency deep spiking neural networks (SNNs) have become a promising alternative to
conventional artificial neural networks (ANNs) because of their potential for increased energy …
conventional artificial neural networks (ANNs) because of their potential for increased energy …
Making models shallow again: Jointly learning to reduce non-linearity and depth for latency-efficient private inference
Large number of ReLU and MAC operations of Deep neural networks make them ill-suited
for latency and compute-efficient private inference. In this paper, we present a model …
for latency and compute-efficient private inference. In this paper, we present a model …
Proteus: An ASIC flow for GHz asynchronous designs
PA Beerel, GD Dimou, AM Lines - IEEE Design & Test of …, 2011 - ieeexplore.ieee.org
Editors' note:The high-performance benefits of asynchronous design have hitherto been
obtained only using full-custom design. This article presents an industrial-strength …
obtained only using full-custom design. This article presents an industrial-strength …
A processing-in-pixel-in-memory paradigm for resource-constrained tinyml applications
The demand to process vast amounts of data generated from state-of-the-art high resolution
cameras has motivated novel energy-efficient on-device AI solutions. Visual data in such …
cameras has motivated novel energy-efficient on-device AI solutions. Visual data in such …
Dnr: A tunable robust pruning framework through dynamic network rewiring of dnns
This paper presents a dynamic network rewiring (DNR) method to generate pruned deep
neural network (DNN) models that are robust against adversarial attacks yet maintain high …
neural network (DNN) models that are robust against adversarial attacks yet maintain high …
Programming memristor arrays with arbitrarily high precision for analog computing
In-memory computing represents an effective method for modeling complex physical
systems that are typically challenging for conventional computing architectures but has been …
systems that are typically challenging for conventional computing architectures but has been …