A 1-V 5.2–5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm CMOS
J Yang, Z Zhang, P Feng, L Liu… - 2015 IEEE 11th …, 2015 - ieeexplore.ieee.org
2015 IEEE 11th International Conference on ASIC (ASICON), 2015•ieeexplore.ieee.org
This paper presents a 5.2-5.7 GHz low voltage sub-sampling phase locked loop (LV-
SSPLL). It adopts a new low voltage multi-modulus frequency divider (LVMMD) based on
Extended True Single-Phase Clock (ETSPC) and TSPC Logic, which can operates at 7 GHz
frequency under only 1V supply voltage in 0.18 μm CMOS process. All the blocks of LV-
SSPLL excluding the output buffer operate at 1V supply voltage. The simulation results show
it consumes only 4.1 mW power. The integrated jitter from 1kHz to 100MHz is 417 fs and …
SSPLL). It adopts a new low voltage multi-modulus frequency divider (LVMMD) based on
Extended True Single-Phase Clock (ETSPC) and TSPC Logic, which can operates at 7 GHz
frequency under only 1V supply voltage in 0.18 μm CMOS process. All the blocks of LV-
SSPLL excluding the output buffer operate at 1V supply voltage. The simulation results show
it consumes only 4.1 mW power. The integrated jitter from 1kHz to 100MHz is 417 fs and …
This paper presents a 5.2-5.7GHz low voltage sub-sampling phase locked loop (LV-SSPLL). It adopts a new low voltage multi-modulus frequency divider (LVMMD) based on Extended True Single-Phase Clock (ETSPC) and TSPC Logic, which can operates at 7 GHz frequency under only 1V supply voltage in 0.18 μm CMOS process. All the blocks of LV-SSPLL excluding the output buffer operate at 1V supply voltage. The simulation results show it consumes only 4.1mW power. The integrated jitter from 1kHz to 100MHz is 417 fs and reference spur is -54dBc when the output frequency is 5.5GHz.
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