This paper attempts to list challenges and possible solutions for designing integrated voltage co... more This paper attempts to list challenges and possible solutions for designing integrated voltage controlled oscillators (VCOs) in wireless products. Such challenges include oscillation frequency, frequency coverage, linearity of tuning curves, phase noise, power consumption, oscillation amplitude variations, sensitivity to process, supply voltage, and temperature variations (PVT), coupling to and from other blocks, start up time, and area. Some design considerations for voltage regulators are also discussed since the noise performance of such regulators can influence the overall design significantly. VCOs in CMOS processes are mainly considered here. An example of taking advantage of modern CMOS processes with active devices with different threshold voltages is also presented.
This session covers fundamental analog building blocks such as voltage references, crystal oscill... more This session covers fundamental analog building blocks such as voltage references, crystal oscillators, inductors, and filters.
Polysilicon surface micromachined varactors using two- and three-plate structures with 1.5:l and ... more Polysilicon surface micromachined varactors using two- and three-plate structures with 1.5:l and 1.87:l tuning ranges, respectively, are presented. The tuning ranges are near-theoretical limits and can be obtained within 4.4 V control voltage. The two-plate varactor has a nominal capacitance of 2.05 pF and a Q-factor of 20 at 1 GHz.
Proceedings ISSCC '95 - International Solid-State Circuits Conference, 2000
This paper presents a 22 kHz, multi-bit D/A converter using a 5-level switched-capacitor (SC) DAC... more This paper presents a 22 kHz, multi-bit D/A converter using a 5-level switched-capacitor (SC) DAC to provide 92 dB dynamic range and better than -94 dB THD. A 4th-order modulator is used with an oversampling ratio of 32. The multi-level SC DAC uses time- and capacitor-multiplexed methods that yield high linearity with a modest opamp gain in the presence of capacitor mismatches. The 5-level DAC is implemented in a double-poly, 2 μm, ±5 V CMOS process from MOSIS without any trimming or calibration
Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 1995
A dynamical associative memory network is experimentally constructed using integrated switched-ca... more A dynamical associative memory network is experimentally constructed using integrated switched-capacitor chaotic neurons. Dynamical retrieval characteristics of memories, which correspond to the chaotic itinerancy, are observed. Network responses with different external stimuli are also investigated
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94, 1994
IC implementation of chaotic neuron using switched capacitor circuit technique is described. Vari... more IC implementation of chaotic neuron using switched capacitor circuit technique is described. Various measured results are presented and interpreted. A new phenomenon called “transient chaos”, which is essential for chaotic simulated annealing, is also demonstrated
This paper attempts to list challenges and possible solutions for designing integrated voltage co... more This paper attempts to list challenges and possible solutions for designing integrated voltage controlled oscillators (VCOs) in wireless products. Such challenges include oscillation frequency, frequency coverage, linearity of tuning curves, phase noise, power consumption, oscillation amplitude variations, sensitivity to process, supply voltage, and temperature variations (PVT), coupling to and from other blocks, start up time, and area. Some design considerations for voltage regulators are also discussed since the noise performance of such regulators can influence the overall design significantly. VCOs in CMOS processes are mainly considered here. An example of taking advantage of modern CMOS processes with active devices with different threshold voltages is also presented.
This session covers fundamental analog building blocks such as voltage references, crystal oscill... more This session covers fundamental analog building blocks such as voltage references, crystal oscillators, inductors, and filters.
Polysilicon surface micromachined varactors using two- and three-plate structures with 1.5:l and ... more Polysilicon surface micromachined varactors using two- and three-plate structures with 1.5:l and 1.87:l tuning ranges, respectively, are presented. The tuning ranges are near-theoretical limits and can be obtained within 4.4 V control voltage. The two-plate varactor has a nominal capacitance of 2.05 pF and a Q-factor of 20 at 1 GHz.
Proceedings ISSCC '95 - International Solid-State Circuits Conference, 2000
This paper presents a 22 kHz, multi-bit D/A converter using a 5-level switched-capacitor (SC) DAC... more This paper presents a 22 kHz, multi-bit D/A converter using a 5-level switched-capacitor (SC) DAC to provide 92 dB dynamic range and better than -94 dB THD. A 4th-order modulator is used with an oversampling ratio of 32. The multi-level SC DAC uses time- and capacitor-multiplexed methods that yield high linearity with a modest opamp gain in the presence of capacitor mismatches. The 5-level DAC is implemented in a double-poly, 2 μm, ±5 V CMOS process from MOSIS without any trimming or calibration
Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 1995
A dynamical associative memory network is experimentally constructed using integrated switched-ca... more A dynamical associative memory network is experimentally constructed using integrated switched-capacitor chaotic neurons. Dynamical retrieval characteristics of memories, which correspond to the chaotic itinerancy, are observed. Network responses with different external stimuli are also investigated
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94, 1994
IC implementation of chaotic neuron using switched capacitor circuit technique is described. Vari... more IC implementation of chaotic neuron using switched capacitor circuit technique is described. Various measured results are presented and interpreted. A new phenomenon called “transient chaos”, which is essential for chaotic simulated annealing, is also demonstrated
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