STA (Static Timing Analysis) Engineer Experience – 3-8 years Location - Hyderabad Technical Skills: Detailed knowledge of EDA tools and flows, Tempus/Primetime experience is must Well-versed with the timing closure (STA), timing closure methodologies Pre/Post-layout constraint development to timing closure Handshake with the design team and develop functional/DFT constraints IP level constraint integration Multi-voltage/Switching aware corner definitions RC/C model selection understanding Abstraction expertise like Hyperscale/ILM/ETM RC Balancing and scaling analysis of full chip clock RC Balancing and scaling analysis of critical data paths Good automation skills in PERL, TCL and EDA tool-specific scripting DMSA @ full chip and custom scripts for timing fixes If you are interested, Please connect with me at [email protected]
Wafer Space - An ACL Digital Company
Semiconductors
Bangalore,, Karnataka 66,053 followers
About us
Wafer Space was founded with the ideals of providing true value in Product Engineering Services to all our clients. Wafer Space is focused in the domains of Semiconductor and Automotive. Our world class engineering team with its intensive knowledge in Chip Design, Automotive embedded software and Embedded product design combined with our ability to execute complex turnkey projects with a steadfast focus on quality is what differentiates us. Wafer Space has one of the industry’s most rigorous selection criteria for engineers which results in a world class engineering team. We strongly believe in continuous learning and growth for all employees. Our organizational culture nurtures creativity and innovation amongst our team players as work no longer is a chore, it’s what we have fun doing! Wafer Space has design centers in Bangalore and Pune India and San Jose, CA, USA. With our proactive client and employee model, Wafer Space is well positioned to deliver quality and timely services to our clientele in Semiconductor and Automotive. Wafer Space Expertise • Semiconductor • RTL Design and Verification • Physical Design and DFT • Turnkey SOC Execution from RTL to GDSII • Custom Verification IP Development • Analog Design, Layout and Verification • Automotive • Product Areas • ADAS • Infotainment • Connectivity • Body Electronics • Safety and Access • BMS • Services • Requirements Engineering • Software Development • Verification and Validation • Rapid Prototyping
- Website
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http://www.waferspace.com
External link for Wafer Space - An ACL Digital Company
- Industry
- Semiconductors
- Company size
- 201-500 employees
- Headquarters
- Bangalore,, Karnataka
- Type
- Privately Held
- Founded
- 2011
- Specialties
- Digital Design and Verification(SOC/IP/VIP), Physical Design, Methodology Consulting, DFT, Turnkey SOC/ASIC Implementation, Embedded Software, Analog Design and Verification, Embedded Systems, Software Development, Automotive, ADAS, AUTOSAR, Automotive Electronics, BMS, Image Processing, and Algorithm Development
Locations
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Primary
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5th Floor, Monarch Ramani, 7th C Main Rd,
Koramangala 3 Block,
Bangalore,, Karnataka 560034, IN
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2880 Zanker Road,
Suite 203,
San Jose,, CA 95134, US
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2020 NW Aloclek Dr, Ste 122
Hillsboro, OR 97124, US
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S. No. 103, Mumbai Banglore Highway, Baner, Mahalunge,
Pune, Maharashtra 411045, IN
Employees at Wafer Space - An ACL Digital Company
Updates
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Finding top talents in Analog Layout,DFT, ASIC RTL Design and STA Engineer's with 3+Yrs of exp to support LeadIC Design growth and continued leadership in Semiconductor.
Hi Everyone!! Wafer Space - An ACL Digital Company is hiring for multiple positions for Bangalore Location!! hashtag #PhysicalDesign Lead : 8+ years (Innovus Tool Experience Required) hashtag #STA Lead : 8+ years hashtag #DFT Lead : 8+ years hashtag #ASIC hashtag #RTLDesign Lead : 8+ Years hashtag #CAD / hashtag #EMIR Engineers : 4 - 6 years hashtag #DFT Engineers : 5+ years hashtag #ASIC hashtag #RTLDesign Engineers : 4-6 years Interested folks please share your resumes' to [email protected]. Wafer Space - An ACL Digital Company ACL Digital