Mulya Technologies

Title Functional Verification Engineer (Top 100 Fortune Organization) Location: Greater Bengaluru Area Your Role and Responsibilities As a Functional Verification Engineer, you will play a crucial role in ensuring the quality and reliability of server processors, SOCs, and ASICs. Guiding the development of verification environments and testbenches, you will be instrumental in crafting test strategies and driving verification coverage closure. Your primary responsibilities include: -Verification Environment Development: Guide the development of verification environments, testbenches, and test cases for IBM server processors, SOCs, and ASICs. -Collaborative Debugging: Collaborate with design teams and key stakeholders to debug and resolve logic design issues, ensuring the delivery of high-quality designs. -Coverage Closure: Drive verification coverage closure by developing comprehensive test plans and strategies, ensuring thorough verification of IP/unit/block-level designs. -Programming: Utilize object-oriented programming skills in C/C++ and scripting languages like Python/Perl to write complex test scenarios and automate verification processes. -Ongoing Skill Development: Develop proficiency in IBM functional verification tools and methodologies, staying updated with the latest advancements in the field. Functional Verification Experience:  -Extensive experience in functional verification of processors or ASICs, demonstrating a deep understanding of verification methodologies. -Computer Architecture Knowledge: In-depth knowledge of computer architecture, including processor core design specifications, instruction set architecture, and logic verification. -Multi-Processor Cache Coherency: Experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. -Gate Level Simulation and Emulation: Proficiency in gate level simulation and emulation techniques, facilitating thorough verification of designs. -Functional Verification Methodology: Expertise in functional verification methodologies such as UVM/OVM/System Verilog/SystemC, ensuring effective verification of designs. Preferred Technical and Professional Experience -Advanced Verification Techniques: Familiarity with advanced verification techniques such as formal verification or assertion-based verification, enhancing verification thoroughness and efficiency. -Experience with Hardware Description Languages (HDLs): Proficiency in hardware description languages like Verilog and VHDL, enabling seamless collaboration with design teams and enhancing verification effectiveness. -Experience in System-Level Verification: Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Preferred Education Master's Degree Interested candidates may submit their CV at [email protected] #verificationjobs #functionalverification #systemlevelverification #cache

We’re #hiring a new SENIOR LOGIC DESIGN ENGINEER – Memory Management Unit in Greater Bengaluru Area. Apply today or share this post with your network.

We’re #hiring a new Senior Design Verification Engineer – Fabric/On Chip Network Verification in Greater Bengaluru Area. Apply today or share this post with your network.

We’re #hiring a new Staff Engineer MTFW Validation, SSDPE in Greater Hyderabad Area. Apply today or share this post with your network.

We’re #hiring a new Staff Engineer MTFW Validation, SSDPE ( Hyderabad ) in Greater Bengaluru Area. Apply today or share this post with your network.

We’re #hiring a new Senior FPGA Engineer in Greater Bengaluru Area. Apply today or share this post with your network.

Title :ASIC/SoC Design Location: Greater Bengaluru Area, Hyderabad, Chennai Company's mission is to secure the end-to-end digital infrastructure by embedding a new breed of hardware-anchored AI-driven platform security in servers, 5G and network infrastructure. Axiado believes data security should be the default solution, not an option. About Company: We are an AI-enhanced security processor company redefining the control and management of every digital system. The company was founded in 2017 and currently has 100+ employees. We are organization where developing great technology takes more than talent: amazing people who understand collaboration, respect each other and go the extra mile to achieve exceptional results. It takes people who have the passion and desire to disrupt the status quo, deliver innovation, and change the world. We invite you to apply for this job if you have this passion. Job Description ASIC/SoC Design position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT. You should have prior knowledge of logic design and computer architecture. As the ASIC/SoC Design Engineer, you will have the opportunity to work in all areas of the SoC design flow. You will work closely with the Architecture, Verification, Physical Design and Software teams, and report to the Director of Engineering. KEY RESPONSIBILITIES -Help develop the design and implementation of SoCs. -Micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks; -Top-level and block-level performance, bandwidth, and power optimization; -Work with FPGA engineers to perform early prototyping; and -Support test program development, chip validation, and chip life until production maturity. -Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development. Qualifications: -8+ years of experience in RTL logic design, verification, synthesis, and timing optimization; -Proficient in writing clear, implementable micro-architecture specifications; -Expertise in writing efficient RTL code in Verilog and SoC integration -Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure; -Should have worked on interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc. -Experience in design bringing up and debugging on FPGA-based emulation platforms like HAPS, and Veloce. -Fluency with scripting languages (e.g., Perl, Python); -Must have gone through at least one tape out. Preferred: -Silicon bring-up and debug experience -Experience in working with repository management tools like Bitbucket/ Jenkins and bug-tracking tools like JIRA. Candidates may share their updated resumes at [email protected] #rtljobs #rtldesign #microarchitecture #socdesign #asic

We’re #hiring a new Senior ASIC RTL Design in Greater Chennai Area. Apply today or share this post with your network.

We’re #hiring a new Lead Hardware Design Engineer (Lead DSP Processor Engineer) in Greater Bengaluru Area. Apply today or share this post with your network.

Accelerator System Architect Top10 Semiconductor Organization in the World Hyderabad / Bangalore Accelerator System Architect We are a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. our Research Center is a part of Technology Pathfinding and Strategy group at India. The goal is to contribute to our pathfinding in multiple areas like Devices and circuits, Systems and AI-ML with enhanced multi-functional collaboration. Role and Responsibilities: Architect, simulate, and design accelerator architecture. You will interact with multi-functional engineering teams to find opportunities and requirements. Some of the job duties include: Implement performance, functional and power model for accelerator architecture exploration and functional verification. Accelerators may include Analog AI using in-memory computing with non-volatile memory technologies. Develop tests, test plans, and testing infrastructure to verify new algorithm and functionality and their performance. Assess new SW/HW innovations and drive the most relevant into the accelerator Architecture definition. Research the industry trend and customer requirement of the machine learning algorithms and accelerators and drive partnerships for access to the most advanced technologies. Qualification and Skills Minimum 12+ years of experience with bachelor’s degree in CS/EE/Math or equivalent. Masters/PhD degree is a big plus. 5+ years of Experience with performance simulation and modeling in modern C++/python. Ability to deliver production quality and well-documented code. Experience in modeling and benchmarking machine learning models on accelerator simulator models. Experience in machine learning frameworks and interfaces, for example: ONNX, TensorFlow and PyTorch. PyTorch is a big plus. Knowledge/Experience in CPU/GPU/Domain Specific Accelerators architecture with a focus on data-path, fixed-point arithmetic, scheduler, memory system, and network-on-chip interconnection design Experiences on NAND Flash Memory and its architecture and circuit design is a big plus. Experiences on DRAM and its architecture and circuit design is a good plus. Experience in approximate compute, analog compute is a good plus. Experience of hardware and RTL implementation (Verilog/System Verilog) is a good plus. Experiences in OpenCL/CUDA/Metal or other such parallel programming APIs is a good plus. Passionate in new technology and innovation with strong communication skills. Job Location : Bangalore/Hyderabad Contact: Sumit Mulya Technologies [email protected]