Aug 21, 2023 · We, for the first time, propose a novel and automated Natural Language Processing (NLP)-based Security Property Generator (NSPG).

Sep 8, 2024 · The paper addresses key areas such as memory management flaws, side-channel attacks, insecure system-on-chip (SoC) resource allocation, and ...

Co-authors ; Unlocking hardware security assurance: The potential of llms. X Meng, A Srivastava, A Arunachalam, A Ray, PH Silva, R Psiakis, ... arXiv preprint ...

In this work we aim to explore the potential of LLMs in the offensive hardware security domain. More specificaly, we explore the level of assistance that LLMs ...

Aug 12, 2024 · LLMs can speed-up the hardware design process from natural language descriptions. Fine-tuned LLMs have the potential to generate better quality Verilog code.

Jun 12, 2024 · This study explores the seeds of LLM integration in register transfer level (RTL) designs, focusing on their capacity for autonomously resolving security- ...

We summarize the resources on LLMs for chip design, focusing on various applications of LLMs, security concerns, and open sources.

Our goal is to outline a roadmap for harnessing the full potential of LLMs in addressing HW security challenges, setting the stage for more robust and secure HW ...

Jun 12, 2024 · We introduce Assert-O, an automated framework designed to derive security properties from SoC documentation and optimize the generated properties.

This paper emphasizes the need for a secure hardware-level foundation for security of these devices, as depending on software security alone is not adequate ...