Thermal Safe High Level Test Synthesis for Hierarchical Testability. High temperature in test process may invalidate a test due to extra delay, or even damage the circuit under test. Therefore, a thermal-safe test can avoid undesirable yield loss due to the extra delay induced by high temperature.
Oct 1, 2009
Experimental results show that the proposed test synthesis method can provide thermal-safe hierarchical test and shorten test application time compared to ...
Tung-Hua Yeh, Sying-Jyan Wang : Thermal Safe High Level Test Synthesis for Hierarchical Testability. Asian Test Symposium 2010: 337-342.
A high-level test synthesis (HLTS) method targeted for delay-fault testability is presented in this paper. The proposed method, when combined with ...
High-level test synthesis: a survey. Hardware · Hardware test · Robustness ... Thermal Safe High Level Test Synthesis for Hierarchical Testability. ATS '10 ...
Since the thermal-aware design cannot achieve thermal-safe hierarchical testing, a thermal-safe high level test synthesis approach is proposed in this paper to ...
Aug 27, 2020 · Testing For Thermal Issues Becomes More Difficult. Chiplets, exotic materials, and heterogeneous integration are impacting test coverage. by ...
Thermal Safe High Level Test Synthesis for Hierarchical Testability · Tung-Hua YehSying-Jyan Wang. Computer Science, Engineering. 2010 19th IEEE Asian Test ...
This thesis details the realisation of on-line testability, in the form of self-checking design, within a high-level synthesis environment. The MOODS (Multiple ...
Dec 1, 2010 · Thermal Safe High Level Test Synthesis for Hierarchical Testability pp. 337-342. A Low Area On-chip Delay Measurement System Using Embedded ...