Abstract: Modern FPGAs can be configured to exploit the large amount of onchip parallelism possible from the distributed SRAM memory blocks for algorithms ...

We develop a C++ API using Vivado High-Level. Synthesis to describe graph computations and generate custom soft processors from these high-level descriptions.

We develop a C++ API using Vivado High-Level Synthesis to describe graph computations and generate custom soft processors from these high-level descriptions.

We develop a C++ API using Vivado High-Level Synthesis to describe graph computations and generate custom soft processors from these high-level descriptions.

We develop a stripped-down soft processor ISA to implement specific repetitive operations on graph nodes and edges that are commonly observed in sparse graph ...

Bibliographic details on Sparse Graph Processing with Soft-Processors.

We develop a stripped-down soft processor ISA to implement specific repetitive operations on graph nodes and edges that are commonly observed in sparse graph ...

We develop a stripped-down soft processor ISA to implement specific repetitive operations on graph nodes and edges that are commonly observed in sparse graph ...

In order to take advantage of GraphStep on a spatial implementation (e.g. FPGA or multi- core processors) we must minimize communication work and latency and ...

This work introduces a concurrent system architecture for sparse graph algorithms that places graph nodes in small distributed memories paired with ...