Selective pseudo scan: combinational ATPG with reduced scan in a full custom RISC microprocessor. Authors: Gopi Ganapathy. Gopi Ganapathy. View Profile. , Jacob ...

Results of applying Selective Pseudo Scan to several complex control blocks of a full custom RISC Microprocessor, demonstrate its superiority compared to ...

SPS consistently showed a higher fault coverage at a much lower CPU time and lower test time than Partial Scan for several control blocks on the RISC.

Apr 25, 2024 · Gopi Ganapathy, Jacob A. Abraham: Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor.

Selective Pseudo Scan - Combinational Atpg with Reduced Scan in a Full Custom Risc Microprocessor pp. 550,551,552,553,554,555. ABLE: AMD Backplane for Layout ...

DAC-1993-GanapathyA #pseudo: Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor ( GG , JAA ), pp. 550–555 ...

Ganapathy and J. A. Abraham, “Selective Pseudo Scan – Combinational ATPG With Reduced Scan. In A Full Custom RISC Microprocessor,” Proceedings 30th IEEE/ACM ...

This paper presents a novel test generation technique, called Selective Pseudo Scan (SPS), which incurs very low overhead. SPS uses a commercial combinational ...

G. Ganapathy and J. Abraham, “Selective Pseudo Scan—Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor”,30th ACM/IEEE Design Automation ...

Selective Pseudo Scan - Combinational Atpg with Reduced Scan in a Full Custom Risc Microprocessor · FALCON: Rapid statistical fault coverage estimation for ...