Oct 20, 2014 · The new access pattern permits to store the intermediate results in block RAM and leads to a compact overall footprint with low register count.

Abstract—Physical Unclonable Functions PUFs are popular se- curity primitives to provide cryptographic keys on FPGAs. However, PUFs require error correction ...

This work presents a highly optimized Viterbi decoder, adapted to the constraints of PUFs on FPGAs, primarily area but also low power. Our Seesaw architecture ...

This work presents a highly optimized Viterbi decoder, adapted to the constraints of PUFs on FPGAs, primarily area but also low power, and demonstrates the ...

Increasing the resistance of a system consisting of several programmable logic integrated circuits (FPGA) to space radiation effects is discussed in the paper.

Our Seesaw architecture contains two block RAMs that are connected through a custom low-area data path. As main result, alternating data access patterns reduce ...

Bibliographic details on Seesaw: An Area-Optimized FPGA Viterbi Decoder for PUFs.

Seesaw: An Area-Optimized FPGA Viterbi Decoder for PUFs. M Hiller, L Rodrigues Lima, G Sigl. Digital System Design (DSD), 2014 17th Euromicro Conference on ...

Seesaw: An Area-Optimized FPGA Viterbi Decoder for PUFs. M Hiller, L Rodrigues Lima, G Sigl. Digital System Design (DSD), 2014 17th Euromicro Conference on ...

This work presents a highly optimized Viterbi decoder, adapted to the constraints of PUFs on FPGAs, primarily area but also low power. Our Seesaw architecture ...