SPAR-2 is a second-generation processor- in/near-memory architecture developed as a programmable over- lay for modern FPGAs. In contrast to point designs, SPAR- 2 can be programmed to implement different classes of ma- chine learning algorithms.
In this paper, SPAR-2, a SIMD processor array for migrating machine learning applications into FPGA IoT edge devices is presented.
Jan 13, 2021 · PDF | In this paper, SPAR-2, a SIMD processor array for migrating machine learning applications into FPGA IoT edge devices is presented.
The sizing and performance analysis of SPAR-2 running a standard Long Short-Term Memory (LSTM) Recurrent Neural Network (RNN) model is provided, ...
Suhail Basalama, Atiyehsadat Panahi, Ange-Thierry Ishimwe, David Andrews : SPAR-2: A SIMD Processor Array for Machine Learning in IoT Devices.
SPAR-2: A SIMD Processor Array for Machine Learning in IoT Devices. S Basalama, A Panahi, AT Ishimwe, D Andrews. 11, 2020 ; A customizable domain-specific memory ...
Ishimwe, (2020) “SPAR-2: A SIMD Processor Array for Machine Learning in IoT Devices.” Proceedings of the 3rd International Conference on Data Intelligence ...
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Oct 7, 2024 · Panahi et al [7, 8, 9] proposed SPAR-2, a SIMD PIM-array overlay accelerator, connecting bit-serial PEs from the programmable fabric with BRAMs.
In this paper, SPAR-2, a SIMD processor array for migrating machine learning applications into FPGA IoT edge devices is presented.
SPAR-2: A SIMD Processor Array for Machine Learning in IoT Devices. DA S Basalama, A Panahi, AT Ishimwe. International Conference on Data Intelligence and ...