The proposed architecture uses error correcting codes (ECC) to tolerate errors in registers and memories, while it employs a combination of space and time redundancy based techniques to tolerate errors in the ALU.
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The proposed architecture uses error correcting codes (ECC) to tolerate errors in registers and memories, while it employs a combination of space and time ...
SHAKTI-F, a RISC-V based SEE-tolerant micro-processor architecture that provides a solution to the reliability issues mentioned above, is presented and ...
This paper presents SHAKTI-F, a RISC-V based SEE-tolerant micro-processor architecture that provides a solution to the reliability issues mentioned above. The ...
... It is fault tolerant version of C-class processor which is RISC based microprocessor. It uses error correcting codes (ECC) to protect registers and memories ...
Jul 2, 2024 · Processor verification incorporates ISA level state checking at every instruction execution along with end of test memory check. ○ Self-checking ...
Jun 7, 2020 · It is a RISC-V based SEE-tolerant microprocessor architecture [1]. Discussing fault tolerant techniques to tackle soft and hard errors and how ...
Nov 1, 2022 · The SHAKTI program offers a software stack, FPGA prototypes, interconnect fabrics, accelerators, device IPs, verification suites, and more under a permissive ...
S. Gupta, N. Gala, G. S. Madhusudan and V. Kamakoti, "SHAKTI-F: A Fault Tolerant Microprocessor Architecture," 2015 IEEE 24th Asian Test Symposium (ATS) ...
The F-class is a fault-tolerant version of the base class processor. ... Shakti-F: A Fault Tolerant Microprocessor Architecture. 2015 IEEE 24th Asian ...