The low leakage in- terconnect via power-gating reduces total power by 38.18% for the FPGA in 100nm technology. Furthermore, it en- ables interconnect dynamic ...

The low leakage interconnect via power-gating reduces total power by 38.18% for the FPGA in 100nm technology. Furthermore, it enables interconnect dynamic power ...

A novel directional coarse-grained power gating architecture for switch boxes is proposed with an average improvement of 22% as compared to the existing VPR ...

The low leakage interconnect via power-gating reduces total power by 38.18% for the FPGA in 100nm technology. Furthermore, it enables interconnect dynamic power ...

Routing Track Duplication with Fine-Grained Power-Gating for FPGA Interconnect Power Reduction Yan Lin, Fei Li and Lei He EE Department, UCLA Partially ...

Routing Track Duplication with Fine-Grained Power-Gating for FPGA Interconnect Power Reduction ... Interconnect Leakage Power Reduction using Power-gating.

Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. DOI PDF 被引用文献1件. Yan Lin · Fei Li · Lei He. 収録刊行物.

We design area-efficient circuits for programmable fine-grained power-gating of individual unused interconnect switches, and reduce interconnect leakage power ...

Authors in Ref. [6] reduced a significant amount of power consumption by fine grain power gating of an FPGA architecture. Furthermore, Leming and Nepal [7] ...

He, "Routing track duplication with fine grained power-gating for FPGA interconnect power reduction," Proc. Asia South Pacific Design Automation Conf., pp ...