This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture.

This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture.

Abstract—This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced ...

This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microprocessor ...

The objective of this research was to demonstrate the ability to design high-speed asynchronous circuits [1] as a potential solution for microprocessor design ...

Abstract—This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design.

This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture.

... RAPPID, a large- scale 120,000-transistor asynchronous version of the Pentium R Pro Instruction Length Decoder, which runs at 3.6 GHz. RAPPID uses a synchronous ...

This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture.

This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture.