In this paper, we give an overview of current on-chip global interconnection structures and provide a sim- ple model to analyze their architecture-level ...

May 10, 2010 · In this paper, we review current on-chip global interconnect structures and develop simple models to analyze their architecture-level ...

The results show that, the T-line structures have the potential to outperform repeated RC wires at future nodes to achieve high-performance, low-power and more ...

The results show that, the T-line structures have the potential to outperform repeated RC wires at future nodes to achieve high-performance, low-power and ...

Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires.

We perform a group of experiments using six different global interconnection structures to discover their differ- ences in terms of latency, energy per bit, ...

In this paper, we review current on-chip global interconnect structures and develop simple models to analyze their architecture-level performance. We propose a ...

Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin , James F. Buckwalter, Chung-Kuan Cheng: Prediction of high-performance on-chip global interconnection.

This study examines the prediction and comparison of performance metrics for on-chip global interconnection schemes, including latency, energy per bit, ...

Download ppt "Prediction of High-Performance On-Chip Global Interconnection Yulei Zhang 1, Xiang Hu 1, Alina Deutsch 2, A. Ege Engin 3 James F. Buckwalter 1, ...