A constant time parallel hierarchical clustering algorithm is proposed on a 3-D processor array with reconfigurable bus system using N 4 processors.

In this paper, we first design twoO[(M2/p2)log logM] andO[(M2/p2)+(M/p)log logp] time parallel image template matching algorithms on a 3-D processor array with ...

Larpbs Model: The linear array with a reconfigurable pipelined bus system (LARPBS) consists of three waveguides. It is presented by Pan and Li in [7]. It is.

Processors arrays with reconfigurable bus systems (abbreviated to PARBS) have been received a lot of attention in the last decade, and many undirected graph ...

Oct 22, 2024 · Similarly, a 3-D processor array for efficient computation solution with flexible reconfigurable bus system was also proposed [29] . A two-stage ...

Efficient Parallel Algorithms for Hierarchical Clustering on Arrays with Reconfigurable Optical Buses · Optimal Speed-Up Parallel Image Template Matching ...

An 0(1) time algorithm for string matching is designed on a two-dimensional (n-m+1)x n processor array with a reconfigurable bus system, where n and m are ...

In this paper we are interested in using processor arrays with a reconfigurable bus system [14] to solve the image template matching problem. All algorithms ...

The main use of this method is to reduce the time spent on comparisons in string matching by using LARPBS. We investigated exact string matching and approximate ...

Jun 1, 1999 · Processors arrays with reconfigurable bus systems (abbreviated to PARBS) have been received a lot of attention in the last decade, ...