In this paper, we show that the instruction cache(I-cache) can adopt the DVS without reliability problems for several reasons. First, an I-cache always stores ...
In this paper, we show that the instruction cache(I-cache) can adopt the DVS without reliability problems for several reasons. First, an I-cache always stores ...
In this paper, the evaluation results show that the drowsy I-cache rarely increases unrecoverable errors and negligibly degrades the performance. 1 Introduction.
The simulation results show that the drowsy instruction cache rarely increases the rate of unrecoverable errors and negligibly degrades the performance, ...
In this paper, we show that the instruction cache(I-cache) can adopt the DVS without reliability problems for several reasons. First, an I-cache always stores ...
Fingerprint. Dive into the research topics of 'On the reliability of drowsy instruction caches'. Together they form a unique fingerprint.
In this paper, we show several reasons why the instruction cache can adopt the drowsy tech- nique without reliability problems. First, an instruction cache ...
Whenever the processor accesses the cache, it compares the block address of the current instruc- tion and checks the validity of the prediction informa-.
Missing: Reliability | Show results with:Reliability
Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink, the dominant ...
shown in Fig.8, the reliability of the drowsy instruction cache approaches that of the normal instruction cache, when the scrubbing period is 1.e6. 6.3 ...