In this paper, we investigate the parameters impacting the SRAM PUF bias of advanced FinFET SRAM designs. In particular, we analyze the bias with respect to ...
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SRAM PUF for FinFET technology nodes 14nm and 7nm considering different temperatures (from 0°C to 85°C), different ramp-up times (from 1µs to 50µs), process.
In particular, we analyze the bias with respect to temperature, mismatches in the power supply network, and ramp-up time. We also consider process variation, ...
In this paper, we investigate the parameters impacting the SRAM PUF bias of advanced FinFET SRAM designs. In particular, we analyze the bias with respect to ...
In this brief, we explore the electrostatics of junctionless accumulation mode (JAM) device with asymmetric spacers to improve the device performance parameters ...
Nov 22, 2023 · SRAM Physical Unclonable Functions (PUFs) are one of the popular forms of PUFs that can be used to generate unique identifiers and ...
Dive into the research topics of 'Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes'. Together they form a unique ...
Rui Wang's 8 research works with 33 citations, including: Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes.
This work evaluates the SRAM PUF reliability using within class Hamming distance (WCHD) for 16nm, 14nm, and 7nm using simulations and silicon validation for ...
Oct 9, 2024 · Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes. ... Modeling Static Noise Margin for FinFET based SRAM ...