This paper presents a new technique which combines variable-threshold (VT) keeper with split-domino (SD) logic technique to improve the power performance.
This paper presents a new technique which combines variable-threshold (VT) keeper with split-domino (SD) logic technique to improve the power performance.
We propose a four-phase non-full swing keeper design to solve this dilemma. Non-full swing switching at the keeper gate together with alleviated contention help ...
We propose a four-phase non-full swing keeper design to solve this dilemma. Non-full swing switching at the keeper gate together with alleviated contention help ...
Domino keeper has to be upsized to keep the noise margin in high fan-in dynamic gates, which increases the power consumption and slows down the evaluation ...
A low power keeper circuit using the concept of rate sensing has been proposed. The proposed technique reduces the amount of short circuit power dissipation ...
These circuit techniques can be classified into two groups. First is the ones propose new keeper circuitry such as high speed domino (HSD) [4], conditional ...
circuit.An LCR keeper to improve the scaling of dynamic gates. The LCR keeper requires an overhead of one FET per dynamic gate plus a portion of a shared ...
ABSTRACT. Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging ...
Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic.