This paper reviews key developments and the continuation of low power techniques needed from the Moore to AI eras. SRAM with a wider range of operation, ...

Abstract—This paper reviews key developments and the continuation of low power techniques needed from the Moore to. AI eras. SRAM with a wider range of ...

Low power design from moore to AI for nm era : Invited paper. Rajiv V. Joshi; Matt Ziegler. 2019; MIXDES 2019. Focus areas. Focus areas. Semiconductors ...

Low power design from moore to AI for nm era : Invited paper. Rajiv V. Joshi ... et al. 2018; CICC 2018. Very low voltage (VLV) design · Ramon Bertran; Pradip ...

This article presents a 7-nm four-core mixed-precision artificial intelligence (AI) chip that supports four compute precisions—FP16, Hybrid-FP8 (HFP8), INT4, ...

Low Power Design From Moore to AI for nm Era (Invited Paper),; Characterization of the Charge-Trap Dynamics in Organic Thin-Film Transistors,; Current vs ...

... Low Power Design from Moore to AI for nm Era,” International. Conference on Mixed Design of Integrated Circuits and Systems (MIXDES), 2019 (Invited). J. Kwon ...

This paper presents a novel resonating inductor-based supply boosting scheme for low-voltage static random-access memories and logic in deep 14-nm silicon ...

Mar 15, 2023 · Abstract. In this paper, we propose a two-stage pipeline architecture for Static Random Memories (SRAM), which can reduce the decoder delay and ...

This paper presents recent advances in low-power AI accelerators over the last four years. Unlike previous surveys on AI accelerators [2,5,7,8,9], this survey ...