Oct 22, 2024 · A DRAM-cell array with 12- F 2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation.
A DRAM-cell array with 12-F 2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation.
Long-Retention-Time, High-Speed DRAM Array with 12-F 2 Twin Cell ...
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Apr 1, 2007 · A DRAM-cell array with 12-F2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and ...
We propose and evaluate a DRAM cell array with 12-F<sup>2</sup> twin cell in terms of speed, retention time, and low-voltage operation. The write time and ...
A DRAM-cell array with 12-F2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation.
Long-retention-time, high-speed DRAM array with 12-F2 twin cell for Sub 1-V operation. IEICE Trans. Electron. (2007). T. Iwai, et al., Low power embedded DRAM ...
Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation. Autores: R. Takemura; Localización: IEICE transactions on electronics ...
May 2, 2013 · A new method is proposed to reduce refresh power consumption dynamically when the full memory capacity is not required, by effectively extending ...
Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation · R. TakemuraK. Itoh +4 authors. T. Kawahara. Engineering, Materials ...
2007: Long-retention-time, high-speed DRAM array with 12-F2 twin cell for sub 1-V operation : Low-power, high-speed LSIs and related technologies Ieice ...