In addition,the integration of VHDL/C co-simulation under the controlof the test bench makes it possible to use the hardware modelfor software testing and vice ...
Hardware/software Co-simulation In A Vhdl-based Test Bench Approach. Published in: Proceedings of the 34th Design Automation Conference. Article #:.
Abstract. Novel test bench techniques are required to cope with a functional test complexity which is predicted to grow much.
Conference PaperPDF Available. Hardware/software Co-simulation In A Vhdl-based Test Bench Approach. July 1997. DOI:10.1109/DAC.1997.597249. Source; IEEE Xplore.
In addition, the integration of VHDL/C co-simulation under the control of the test bench makes it possible to use the hardware model for software testing and ...
Hardware/Software Co-Simulation in a VHDL-Based Test Bench ...
www.tib.eu › BLCP:CN020606025 › Har...
Title: Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach · Contributors: Bauer, M. · Conference: 34th, Design automation conference ; 1997 ; ...
PDF | We describe a technique for hardware-software co-simulation that is almost cycle-accurate, and does nor require the use of interprocess.
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What is a VHDL test bench?
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In hardware-assisted simulation, a high-powered co-processor is used to execute the simulation of the gate-level model. Other parts of the simulation, such as ...
Aug 2, 2010 · My suggestion: just use ModelSim by itself. Create a new project, load all you VHDL (testbench and rtl) and simulate it. IIRC, with ModelSim- ...
This approach addresses the modeling of communication between the hardware and software modules at different abstraction levels and for different design tools.