An interim report on the experimental fault-tolerance verification of the onboard space computer loaded on the artificial satellite Hiten is presented.
Fault-Tolerance Experiments of the "Hiten" Onboard Space Computer. Tadashi Takano+, Takahiro Yamada+, Kohshiroh Shutoh*, and Nobuyasu Kanekawa++. +: Institute ...
An interim report on the experimental fault-tolerance verification of the onboard space computer loaded on the artificial satellite Hiten is presented, ...
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The CRC ARGOS project involves fault tolerance experiments conducted on a ... Kanekawa, “Fault-Tolerance. Experiments of the 'Hiten' Onboard Space Computer,” Dig.
The main mission objectives of the Hiten mission include several demonstrations of engineering technologies: (1) Trajectory-control, acquisition and ...
The onboard command computer consists of three independent processor cells with a total of 2 Mbits ROM and 512 Kbits RAM. Mission Profile. Hiten was launched ...
Tadashi Takano, Takahiro Yamada, Kohshiroh Shutoh, Nobuyasu Kanekawa: Fault Tolerance Experiments of the "Hiten" Onboard Space Computer. FTCS 1991: 26-35.
System fault-tolerance analysis of COTS-based satellite on-board computers ... In-orbit experiment on the fault-tolerant space computer aboard the satellite Hiten.
The paper discusses the Japanese first lunar mission named “Hiten”. The spacecraft system, its major mission objectives, namely, the double lunar swingby ...
FaultTolerance Testing in the Advanced Automation System. 18. FaultTolerance Experiments of the Hiten Onboard Space Computer. 26. A Path Oriented Scheme for ...