In the paper a possibility of evolutionary number of gate optimization in PLA circuits implemented in VLSI technology is presented.
In this paper, the evolutionary optimization of gate number in PLA circuits realized in VLSI technology is presented. Multi-layer chromosomes [7, 8] have been ...
In the paper a possibility of evolutionary number of gate optimization in PLA circuits implemented in VLSI technology is presented.
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This work presents a procedure to automate the design of Si-integrated radio frequency (RF) discrete tuning varactors (RFDTVs).
Software evolution. Recommendations. Evolutionary Optimization of Number of Gates in PLA Circuits Implemented in VLSI Circuits. EvoWorkshops '09: Proceedings ...
The logical expression assigned for implementation in PLA circuits is optimized with respect to minimal number of logical products existing in this expression ...
Jun 14, 2024 · The PLA encoding is then converted, synthesized and mapped to a minimal technology library of inverter and 2-input NOR gates by abc. The ...
In this paper an approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested.
Missing: Optimization | Show results with:Optimization
This work presents an optimization method for the synthesis of finite state machines. The focus is on the reduction in the on- chip area and the cost of the ...
In this study, a new single layer design of PLA in QCA is suggested. The proposed circuit is evaluated in terms of area, latency, cell numbers, and logic gates ...
Missing: Evolutionary Optimization