Feb 13, 2017 · The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back ...
Abstract: This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked ...
Facing this, we present a novel cost-effective DNU (let alone SNU) resilient latch design in nanoscale CMOS technology. Simulation results have demonstrated the ...
This paper presents a novel low cost and double node upset tolerant latch design in 22nm CMOS technology. The latch mainly comprises a single node upset ...
A Radiation-Hardened Double Node Upset Latch Design for ...
www.semanticscholar.org › paper › A-Ra...
This paper presents a newly designed latch which provides resilience to double node upsets (DNU) caused by radiations like alpha or harmful rays.
Aug 8, 2022 · The proposed latch overcomes the architecture and performance limitations of state-of-the-art double-node-upset (DNU)-resilient latches.
In this paper, we propose a novel high reliability and low cost DNU (Double Node Upset) tolerant latch, HRCE (High Robust and Cost Effective) latch, ...
A novel highly robust hardened latch design is presented that is fully resilient to single event double node upsets and single node upsets. The proposed latch ...
CMOS. Conference Paper. Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology. November 2016. DOI:10.1109/ATS.2016.17.
Nov 30, 2023 · This paper proposes a double-node upset complete resilient (DNUCR) latch to meet the requirements of low orbit space applications for high ...