To make FPGA application development easier, firstly, we propose a methodology that provides clean abstractions with high-level APIs and a simple execution ...

To improve device utilization and share the FPGA among multiple users, a lightweight runtime system is developed that provides hardware-assisted memory ...

Section III presents the hardware infrastructure. Section IV focuses on the runtime manager architecture and features. Section V describes the design flow we ...

Hypervisor creates an abstraction layer between software applications and the underlying FPGA hardware and manages the vFPGA resources.

To make FPGA application development easier, firstly, we propose a methodology that provides clean abstractions with high-level APIs and a simple execution ...

In this paper, we illustrate how these features can be developed in a lightweight manner and quantitatively evaluate the performance overhead they introduce on ...

Fingerprint. Dive into the research topics of 'Designing a virtual runtime for FPGA accelerators in the cloud'. Together they form a unique fingerprint.

In the cloud context, the ability to modify accelerator functions at runtime in a multi-user environment is essential. This requires new techniques in hardware ...

In this study, we conducted an in-depth investigation of the technologies used in FPGA-based DNN accelerators, including but not limited to architectural design ...

Dec 1, 2021 · Hardware-accelerated cloud computing systems based on FPGA chips (FPGA cloud) or ASIC chips (ASIC cloud) have emerged as a new technology ...