The simulation results show that the proposed ISEHL latch can not only be applied to clock-gating circuits but also perform with 41% power as well as 95% Power ...

The simulation results show that the proposed ISEHL latch can not only be applied to clock-gating circuits but also perform with 41% power as well as 95% ...

Jul 2, 2019 · In this paper, a low-power and high-speed single event upset radiation hardened latch is proposed. The proposed latch can withstand single event ...

Sep 27, 2024 · This paper proposes two quadruple-node-upset hardened latches: 4DICE-C and 4DICE-V. These two latches are both based on dual-interlocked-storage-cell (DICE)

Bibliographic details on Design of a Radiation Hardened Latch for Low-Power Circuits.

Nov 16, 2014 · The proposed latch is based on three C-elements which are errors tolerable, and the logic state of each C-element is determined by the output ...

Compared with all alternative structures, TNUL is the best in terms of delay and PDP. Compared to other TNU tolerant latches, TNUL achieves a suboptimal power ...

In this work, a radiation hardened latch based on NMOS only Schmitt trigger with voltage booster (NST-VB) is proposed. We first analyze the critical charge at ...

Jun 18, 2024 · In this work, radiation-hardened, self-healing latch designs are presented that can effectively deal with single event upsets (SEUs) by keeping ...

Oct 22, 2024 · The Cascode ST latch has 112% higher critical charge than the conventional reference latch with only 10% area increase. A novel design metric ( ...