This paper presents a comprehensive model for estimation and optimization of the delay in submicron digital CMOS circuits. Our delay model for a logic gate ...

Delay optimization of a critical path is performed by solving a set of non-linear transistor sizing formulas using iteration. Very good agreement is observed.

Our delay model for a logic gate depends on the topology of the gate, the size and topology of the preceding gate, and the load. This model is explicit in terms ...

This paper presents a unified model for delay estimation in various CMOS logic styles. It also derives closed-form optimal transistor sizing formulas for ...

Close form solutions for the output voltage and short-circuit power of a CMOS gate driving an LC transmission line are presented and agree with circuit ...

Abstract-Controlling RC interconnection delay is the key to high-speed VLSI designs [1], [2]. In this paper, a closed-form formula for a waveform of the RC line ...

... closed form analytical expression characterizing the propagation delay of a CMOS inverter to be developed. In the following analysis, analytical expressions ...

These expres- sions are used to estimate the propagation delay and the rise and fall times (or transition times) of a CMOS inverter. Since the output waveform ...

It also introduces a simple expression for MOSFET saturation current and derives closed-form optimal transistor sizing formulas for minimizing the delay in each ...

d) Do not provide a closed form expression for the delay – Several works must evaluate the out- put voltage as function of time in order to estimate the delay.