Our hybrid cache hierarchy chooses different memory technologies to configure each level so that the bandwidth provided by the overall hierarchy is optimized.

We will present a reconfiguration mechanism to dynamically adapt the space of each cache level to the demand of different applications. Emerging memory ...

Dec 11, 2013 · We name our persistent memory design Kiln, because it is analogous to persistent memory which turns volatile data into permanent records.

Bibliographic details on Bandwidth-aware reconfigurable cache design with hybrid memory technologies.

In this paper, we propose a bandwidth-aware re-configurable cache hierarchy (BARCH) with hybrid memory technologies. BARCH consists of a hybrid cache hierarchy, ...

In this paper, we address this problem by proposing a memory, a bandwidth-aware reconfigurable cache hierarchy, BACH, with hybrid memory technologies.

• Using different memory technologies to improve the bandwidth of caches with large capacities. • A bandwidth-aware reconfigurable hybrid cache hierarchy to.

Our hybrid cache hierarchy chooses different memory technologies with various bandwidth characteristics, such as spin-transfer torque memory (STT-MRAM), ...

Usage Metrics of. Bandwidth-aware reconfigurable cache design with hybrid memory technologies. Author(s): Zhao, Jishen ; Xu, Cong ; Xie, Yuan. Source: IEEE/ACM ...

NVRAMs promise high-bandwidth cache solutions for CMPs. We propose a bandwidth-aware reconfigurable cache hierarchy with hybrid memory technologies. With ...