Aug 28, 2014 · The equalizer demonstrates successful operation with variable data-rates ranging from 10 Gb/s to 25 Gb/s and power dissipation scalable from 55 mW to 90 mW.

Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS · 25 Citations · 27 References.

Realized in 28 nm LP CMOS tech- nology, core silicon area is only 0.086 mm and measurements prove successful equalization from 10 Gb/s to 25 Gb/s with power ...

Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS.

A new all-pass stage is proposed to realize a delay line suitable for high-speed operation while being able to accommodate large input signal amplitude.

This paper presents a 25-Gb/s FIR equalizer in 28-nm CMOS. The impact of filter noise and distortion, crucial aspects for an analog implementation, is discussed ...

Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS. Article. Aug 2014.

The equalization capability has been verified at different data rate (from 10 to. 25Gb/s) by emulating a MMF channel. Furthermore the FIR is tested at 10Gb/s.

This paper presents a power scalable clock data recovery (CDR) suitable for multilane and multirate applications. To make the power consumption scale with ...

Dec 13, 2023 · Exploiting ultra-wide bandwidths is a promising approach to achieve the terabits per second (Tbps) data rates required to unlock emerging ...