Jan 2, 2023 · We propose an efficient parallel hardware architecture, which uses a new sorting circuit with a ping-pong buffer and a new retention mechanism of the candidate ...

Jun 8, 2023 · Experiments indi- cated that the algorithm runs on the chip with area of 0.75mm2, power consumption of 68.41 mW, and normalized area efficiency.

Oct 22, 2024 · This architecture uses a PE group with a voting mechanism to simplify the algorithm for reducing the latency and area. Additionally, the PE ...

Non-maximum suppression (NMS) is an indispensable post-processing step in object detection. With the continuous optimization of network models, NMS has become ...

Nov 26, 2024 · This paper systematically analyzes NMS from a graph theory perspective for the first time, revealing its intrinsic structure.

An efficient, mask-size independent algorithm for the maxi- mum filter was proposed by Gil and Werman [1]. Given the maximum filter response in each pixel, the ...

In this paper, we propose a vision-based feature tracker for the autonomous hovering of an unmanned aerial vehicle (UAV) and present an area-efficient hardware ...

This leads to an Accelerated NMS algorithm which leverages Spatially Aware Priors, or ASAP-NMS, and improves the latency of the NMS step from 13.6ms to 1.2 ms ...

Contribution 2: Scalable Hardware Acceleration of Non- Maximum Suppression In this contribution, we present ShapoolNMS, a scalable and parallelizable ...

Dec 5, 2024 · During the inference phase, post process involves choosing bounding boxes that represent true targets using Non Maximum Suppression (NMS). As ...