State-of-the-art RAM chips are invariably reconfigurable. After reconfiguration, the logical neighborhood of the memory cells may no longer be same as the ...

Section 3 shows how the widely used MSCAN and Marching Tests can be used to test a reconfigured linear array for physical neighbor- hood PSFs. Section 4 shows ...

A test algorithm is presented that detects static five-cell physical neighborhood pattern sensitive faults in reconfigured RAMs and RAMs with scrambled ...

Hypergraph Coloring and Reconfigured RAM Testing. RAM decoders are designed with a view to minimize the overall silicon area and critical path lengths. · A RAM ...

We give three new algorithms to compute tests for faults in the interconnects of random access memories (RAM) using only read and write operations. Diagnosis of ...

This paper proposes a reconfigurable BISTR (ReBISTR) scheme to test repairing RAMs with different sizes and redundancy organizations. ... algorithm for various ...

This paper presents the philosophy and design of a fault-tolerant dynamically-reconfigurable random access memory (RAM) system with a built-in ...

After a memory chip is reconfigured, physically adjacent cells may no longer have consecutive logical addresses. Test algorithms used at later stages for the ...

These algorithms have test lengths of O(Nr10g3M4) for N-bit RAMs, and also detect other faults such as stuck-at and coupling faults. The algorithms depend on ...

This paper presents a reconfigurable BISR (ReBISR) scheme for repairing RAMs with different sizes and redundancy organizations. An efficient redundancy analysis ...