The folding technique consists in connecting parallel transistors with reduced channel width to achieve a large overall width. Given a transistor with a channel width W, the same W/L ratio, thus the same drive strength, can be achieved by connecting n transistors with width W/n.
A technique for pull-up transistor folding. Abstract: The authors consider the constraint limiting multiple folding in programmable logic array (PLA) layouts ...
Abstract-One of the constraints limiting multiple folding in PLA layouts is the layout architecture which positions pull-up transistors on.
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What is transistor folding?
What is pull up transistor?
In this paper, we present a novel architecture supporting multiple I/O, term, and pull-up foldings with through-the-cell net routing. The pull-up folding allows ...
A pull-down transistor is created by crossing a diffusion Iine with a polysilicon line. The pull-up transistors are placed outside, usually, on the left or on ...
Apr 1, 2021 · The folding technique has been equally applied to both pull-up and pull-down networks. To study the impact of asymmetric designs, the 2-finger ...
The folding technique has been equally applied to both pull-up and pull-down networks. To study the impact of asymmetric designs, the 2-finger design and the 4- ...
A new folding algorithm applied to an automatic layout generation tool that is able to obtain very good results and is based on a very simple algorithm.
Oct 22, 2024 · Accordingly, this work analyzes the efficiency of transistor folding layout in improving the Single-Event Transient robustness of digital ...
Apr 16, 2012 · Summarised Solution: The two configurations are close to equivalent. Either would work equally well in almost all cases.