The experimental results show that the proposed multiplier is 2 times faster than the serial LFSR multiplier with the same number of registers. The low power ...
A fast-serial finite field multiplier without increasing the number of ...
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the proposed architecture can achieve fast multiplication without increasing the number of registers by sharing the result register for even and odd bits ...
Wonjong Kim, Seungchul Kim, Hanjin Cho, Kwang-youb Lee: A fast-serial finite field multiplier without increasing the number of registers.
Bibliographic details on A fast-serial finite field multiplier without increasing the number of registers.
This way, the number of clock cycles for one field multiplication is reduced by a factor of two. Similarly, we can extend this idea to build a multiplier that ...
It is concluded in this article that the dual basis multiplier needs the least number of gates, which in turn leads to the smallest area required for VLSI ...
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Jul 2, 2015 · Abstract—The paper presents details on fast and secure. GF(2m) multipliers dedicated to elliptic curve cryptography applications.
It is possible to modify any finite field multiplier to allow for serial-serial behavior (e.g. by adding serial-to-parallel and parallel-to-serial registers).
A fast-serial finite field multiplier without increasing the number of registers ... faster than the serial LFSR multiplier with the same number of registers.
In this paper, a modified interleaved modular reduction multiplication algorithm and its bit-serial sequential architecture are proposed. It is observed from ...
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