In this paper, we present an area-efficient 4/8/16/32-point inverse discrete cosine transform (IDCT) architecture for a HEVC decoder.

This work reduces the hardware cost of 1D IDCT by proposing a reordered parallel-in serial-out (RPISO) scheme, and reduces the logical costs of 1D IDCT by ...

*The material contained in this document is based upon work supported by a National Aeronautics and Space Administration (NASA) grant or cooperative agreement.

In this paper, we present an area-efficient 4/8/16/32-point inverse discrete cosine transform (IDCT) architecture for a HEVC decoder.

Oct 22, 2024 · In this paper, we present an area-efficient 4/8/16/32-point inverse discrete cosine transform (IDCT) architecture for a HEVC decoder.

Fingerprint. Dive into the research topics of 'A low-cost VLSI architecture of multiple-Size IDCT for H.265/HEVC'. Together they form a unique fingerprint.

Dec 1, 2014 · In this paper, we present an area-efficient 4/8/16/32-point inverse discrete cosine transform (IDCT) architecture for a HEVC decoder. Compared ...

Due to the high complexity of the existing hardware implementation, this paper presents the low-cost and efficient DCT architectures for HEVC, which are able to ...

Nov 30, 2020 · In this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple ...

Nov 13, 2014 · This paper describes a novel design methodology for the 2D inverse transform used in the H.265/HEVC hardware decoder and encoder. To support ...