A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumps. Abstract: In the interest of extending battery life in mobile ...

Feb 10, 2009 · To amplify the residue in each pipeline stage without opamps, a technique inspired by capacitive charge-pumps is used. In capacitive charge- ...

A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumps · I. Ahmed, J. Mulder, D. Johns · Published in IEEE International Solid…

A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumps. March 2009. DOI:10.1109/ISSCC.2009.4977359. Source; IEEE Xplore.

This work presents a low power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in a 180nm silicon based CMOS process. Simultaneous capacitor sharing and ...

A 50MS/s 9.9mW Pipelined ADC with. 58dB SNDR i 0 18. CMOS U i. 58dB SNDR in 0.18µm CMOS Using. Capacitive Charge-Pumps. Imran Ahmed1,3, Jan Mulder2, David A ...

... A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumps. Ahmed I., Mulder J., Johns D.A.. Expand. Publication type ...

A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumps. Conference Paper. Mar 2009. Imran Ahmed · Jan ...

Feb 9, 2010 · Ahmed, J. Mulder, and D. A. Johns, “A 50MS/s 9.9mW Pipelined ADC with. 58dB SNDR in 0.18µm CMOS Using Capacitive Charge-Pumps, ...

A 50MS/s 9.9 mW pipelined ADC with 58dB SNDR in 0.18 µm CMOS using capacitive charge-pumps. I Ahmed, J Mulder, DA Johns. 2009 IEEE International Solid-State ...