Abstract: A scaling-friendly and energy-efficient 0-1 MASH ΔΣ ADC is proposed in this work. An 8b SAR is used as the 1st stage for coarse quantization.
The proposed ADC uses digital background calibration to track VCO gain variation across. PVT. A 40nm CMOS prototype achieves a Walden FoM of. 18.5 fJ/conv-step ...
Missing: ΔΣ | Show results with:ΔΣ
A scaling-friendly and energy-efficient 0-1 MASH ΔΣ ADC is proposed in this work that uses digital background calibration to track VCO gain variation across ...
Sep 21, 2016 · The proposed ADC uses digital background calibration to track VCO gain variation across PVT. A 40nm CMOS prototype achieves a Walden FoM of 18.5 ...
A 18.5-fJ/step VCO-based 0–1 MASH ΔΣ ADC with digital background ...
www.researchgate.net › ... › ADC
Open-loop VCO-based ADCs with digital calibration have solved this problem [53] but suffer from complicated design. The closed-loop structure calls for a ...
A 18.5-fJ/step VCO-based 0–1 MASH ΔΣ ADC with digital background calibration. A Sanyal, N Sun. 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016.
Bibliographic details on A 18.5-fJ/step VCO-based 0-1 MASH ΔΣ ADC with digital background calibration.
Hybrid VCO Based 0-1 MASH and Hybrid ΔΣ SAR. @inproceedings ... A 18.5-fJ/step VCO-based 0–1 MASH ΔΣ ADC with digital background calibration.
A 18.5-fJ/step VCO-based 0–1 MASH ΔΣ ADC with digital background calibration. Conference Paper. Jun 2016. Arindam Sanyal · Nan Sun · View.
A 18.5-fJ/step VCO-based 0–1 MASH ΔΣ ADC with digital background calibration. DOI PDF 被引用文献1件. Arindam Sanyal · Nan Sun. 収録刊行物.