This work presents a 1.40mm 2 40nm CMOS sparse neuromorphic processor that implements a two-layer convolutional restricted Boltzmann machine (CRBM) for ...

A 1.40mm2 sparse neuromorphic processor (Fig. 5) is implemented in. 40nm CMOS. The chip uses 40Kb registers to store weights and 12Kb registers to queue L2 ...

This work presents a 1.40mm2 40nm CMOS sparse neuromorphic processor that implements a two-layer convolutional restricted Boltzmann machine (CRBM) for ...

TL;DR: This work presents a 1.40mm2 40nm CMOS sparse neuromorphic processor that implements a two-layer convolutional restricted Boltzmann machine (CRBM) ...

A 1.40mm2 141mW 898GOPS sparse neuromorphic processor in 40nm CMOS. Knag, Phil, Chester Liu, Zhengya Zhang · Details · Contributors · Bibliography · Quotations ...

Knag, et al., "A 1.40mm2 141mW 898GOPS Sparse Neuromorphic Processor in 40nm CMOS", In IEEE Symposium on VLSI Circuits, Jun. 15, 2016, 2 Pages. Kumar, Samir ...

Zhang, “A 1.40mm2 141mW 898GOPS sparse neuromorphic processor in 40nm CMOS,” in Symp. VLSI Circuits, Honolulu, HI, Jun. 2016. [C34] S. Sun and Z. Zhang ...

Prevent memory fetches and MAC operations based on the ReLU sparsity. A 1.40mm2 141mW 898GOPS Sparse Neuromorphic Processor in 40nm CMOS. (University of ...

First neuromorphic processor with on-chip learning capabilities. Spike signals ... A 1.40 mm2 141 mW 898GOPS sparse neuromorphic processor in 40 nm CMOS ...

A 1.40mm2 141mW 898GOPS sparse neuromorphic processor in 40nm CMOS · Phil C. KnagChester LiuZhengya Zhang. Computer Science, Engineering. 2016 IEEE Symposium on ...