A 0.6-to-200MSPS speed reconfigurable 0.49pJ/conversion 10bit ADC is implemented in a 90nm digital CMOS process. The proposed technique configures the ADC ...

This paper presented a speed-reconfigurable power- scalable 10bit ADC. The ADC speed can be programmed from 0.6MSPS up to 200MSPS, with power scalable from 1.9 ...

The paper presents a reconfigurable Delta-Sigma Modulator suitable for three operation modes, whose application ranges from bio-potential signal monitoring ...

A 0.6-to-200MSPS speed reconfigurable 0.49pJ/conversion 10bit ADC is implemented in a 90nm digital CMOS process. The proposed technique configures the ADC ...

A 0.6-to-200MSPS speed reconfigurable and 1.9-to-27mW power scalable 10bit ADC. H. Zhang, J. Tan, C. Zhang, H. Chen, and E. Sánchez-Sinencio.

A 0.6-to-200MSPS speed reconfigurable 0.49pJ/conversion 10bit ADC is implemented in a 90nm digital CMOS process. The proposed technique configures the ADC ...

Sánchez-Sinencio, “A 0.6-to-200MSPS Speed Reconfigurable and 1.9-to-27mW Power Scalable 10bit ADC”, IEEE European Solid State Circuits Conference, pp. 367 ...

Oct 22, 2024 · This paper presents a low power, variable resolution ADC which can configure its resolution depending upon the present channel conditions.

A 0.6-to-200MSPS speed reconfigurable and 1.9-to-27mW power scalable 10bit ADC. ESSCIRC 2011: 367-370. [+][–]. Coauthor network. maximize. Note that this ...

A 0.6-to-200MSPS speed reconfigurable and 1.9-to-27mW power scalable 10bit ADC · Computer Science, Engineering. 2011 Proceedings of the ESSCIRC (ESSCIRC) · 2011.