This paper describes the design of a 25Gb/s 2-level digital serial line receiver including a ¼-rate 5b flash ADC, an 8-tap feed-forward equalizer (FFE), an 8- ...
The AFE is fabricated in 0.18 μm 1P6M CMOS process. The core chip size of the AFE without I/O pads is 4000 by 4500 μm2. The input referred noise is measured to ...
Feb 1, 2016 · As CMOS devices continue to scale down in voltage and area, digital-based high- speed serial I/Os [1] become increasingly competitive with ...
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32 References · 3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI · 3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS.
3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI. S Rylov, T Beukema, Z Toprak-Deniz, T Toifl, Y Liu, A Agrawal, ... 2016 IEEE International Solid- ...
CMOS ADC-based serial link receivers enable powerful digital equalization and symbol detection techniques for high data rate operation over electrical and ...
Rylov S, Beukema T, Deniz ZT, et al. 3.1 A 25Gb/s ADC–based serial line receiver in 32nm CMOS SOI. Solid–State Circuits Conference (ISSCC), 2016 IEEE ...
3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI · 10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface.
Aug 24, 2022 · Leblebici, “A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous. SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS,”.
[15] S. Rylov et al., "3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI," 2016. IEEE International Solid-State Circuits Conference (ISSCC), 2016 ...